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Searched refs:PLL_PLLDV_ODIV2_MASK (Results 1 – 3 of 3) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32k3/BaseNXP/header/
DS32K344_PLL.h145 #define PLL_PLLDV_ODIV2_MASK (0x7E000000U) macro
148 … (((uint32_t)(((uint32_t)(x)) << PLL_PLLDV_ODIV2_SHIFT)) & PLL_PLLDV_ODIV2_MASK)
/hal_nxp-3.5.0/s32/drivers/s32k3/Mcu/src/
DClock_Ip_Divider.c275 RegValue &= ~PLL_PLLDV_ODIV2_MASK; in Clock_Ip_SetPllPlldvOdiv2Output()
DClock_Ip_Frequency.c1820 uint32 DividerValue = (IP_PLL->PLLDV & PLL_PLLDV_ODIV2_MASK) >> PLL_PLLDV_ODIV2_SHIFT; in Clock_Ip_Get_PLL_POSTDIV_CLK_Frequency()
1835 uint32 DividerValue = (IP_PLL_AUX->PLLDV & PLL_PLLDV_ODIV2_MASK) >> PLL_PLLDV_ODIV2_SHIFT; in Clock_Ip_Get_PLLAUX_POSTDIV_CLK_Frequency()