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Searched refs:PLLDIG_PLLODIV_DIV_MASK (Results 1 – 3 of 3) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_PLLDIG.h204 #define PLLDIG_PLLODIV_DIV_MASK (0xFF0000U) macro
207 … (((uint32_t)(((uint32_t)(x)) << PLLDIG_PLLODIV_DIV_SHIFT)) & PLLDIG_PLLODIV_DIV_MASK)
/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Divider.c280 RegValue &= ~PLLDIG_PLLODIV_DIV_MASK; in Clock_Ip_SetPlldigPll0divDeDivOutput()
DClock_Ip_Frequency.c1415 …Frequency /= (((IP_CORE_PLL->PLLODIV[0U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT) +… in Clock_Ip_Get_COREPLL_PHI0_Frequency()
1484 …Frequency /= (((IP_PERIPH_PLL->PLLODIV[0U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT)… in Clock_Ip_Get_PERIPHPLL_PHI0_Frequency()
1493 …Frequency /= (((IP_PERIPH_PLL->PLLODIV[1U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT)… in Clock_Ip_Get_PERIPHPLL_PHI1_Frequency()
1501 …Frequency /= (((IP_PERIPH_PLL->PLLODIV[2U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT)… in Clock_Ip_Get_PERIPHPLL_PHI2_Frequency()
1509 …Frequency /= (((IP_PERIPH_PLL->PLLODIV[3U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT)… in Clock_Ip_Get_PERIPHPLL_PHI3_Frequency()
1517 …Frequency /= (((IP_PERIPH_PLL->PLLODIV[4U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT)… in Clock_Ip_Get_PERIPHPLL_PHI4_Frequency()
1525 …Frequency /= (((IP_PERIPH_PLL->PLLODIV[5U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT)… in Clock_Ip_Get_PERIPHPLL_PHI5_Frequency()
1533 …Frequency /= (((IP_PERIPH_PLL->PLLODIV[6U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT)… in Clock_Ip_Get_PERIPHPLL_PHI6_Frequency()
1602 …Frequency /= (((IP_DDR_PLL->PLLODIV[0U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT) + … in Clock_Ip_Get_DDRPLL_PHI0_Frequency()