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Searched refs:PIT0PCTL (Results 1 – 2 of 2) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_GPR3_PCTL.h100 …__IO uint32_t PIT0PCTL; /**< CE_PIT_0 Clock Control Enable, offset: 0x6C … member
/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Frequency.c2321 …Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->PIT0PCTL & GPR3_PCTL_PIT0PCTL_PCTL_MASK) >> GP… in Clock_Ip_Get_CE_PIT0_CLK_Frequency()