MUX_9_DC_1 (reference) in projects: hal_nxp-3.5.0

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Searched refs:MUX_9_DC_1 (Results 1 – 2 of 2) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/src/
D	Clock_Ip_Frequency.c	3267 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_9_DC_1 & MC_CGM_MUX_9_DC_1_DE_MASK) >> … in Clock_Ip_Get_ETH1_RX_RGMII_CLK_Frequency() 3268 …Frequency /= (((IP_MC_CGM_1->MUX_9_DC_1 & MC_CGM_MUX_9_DC_1_DIV_MASK) >> MC_CGM_MUX_9_DC_1_DIV_SHI… in Clock_Ip_Get_ETH1_RX_RGMII_CLK_Frequency() 3573 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_9_DC_1 & MC_CGM_MUX_9_DC_1_DE_MASK) >> … in Clock_Ip_Get_P4_QSPI1_2X_CLK_Frequency() 3574 …Frequency /= (((IP_MC_CGM_4->MUX_9_DC_1 & MC_CGM_MUX_9_DC_1_DIV_MASK) >> MC_CGM_MUX_9_DC_1_DIV_SHI… in Clock_Ip_Get_P4_QSPI1_2X_CLK_Frequency() 3583 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_9_DC_1 & MC_CGM_MUX_9_DC_1_DE_MASK) >> … in Clock_Ip_Get_P4_QSPI1_1X_CLK_Frequency() 3584 …Frequency /= ((((IP_MC_CGM_4->MUX_9_DC_1 & MC_CGM_MUX_9_DC_1_DIV_MASK) >> MC_CGM_MUX_9_DC_1_DIV_SH… in Clock_Ip_Get_P4_QSPI1_1X_CLK_Frequency() 3788 …Frequency /= ((((IP_MC_CGM_4->MUX_9_DC_1 & MC_CGM_MUX_9_DC_1_DIV_MASK) >> MC_CGM_MUX_9_DC_1_DIV_SH… in Clock_Ip_Get_QSPI1_CLK_Frequency()
/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/
D	S32Z2_MC_CGM.h	`157 …__IO uint32_t MUX_9_DC_1; /**< Clock Mux 9 Divider 1 Control Register, offs… member`

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