MUX_8_DC_1 (reference) in projects: hal_nxp-3.5.0

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Searched refs:MUX_8_DC_1 (Results 1 – 2 of 2) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/src/
D	Clock_Ip_Frequency.c	3287 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_8_DC_1 & MC_CGM_MUX_8_DC_1_DE_MASK) >> … in Clock_Ip_Get_ETH1_TX_RGMII_CLK_Frequency() 3288 …Frequency /= (((IP_MC_CGM_1->MUX_8_DC_1 & MC_CGM_MUX_8_DC_1_DIV_MASK) >> MC_CGM_MUX_8_DC_1_DIV_SHI… in Clock_Ip_Get_ETH1_TX_RGMII_CLK_Frequency() 3297 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_8_DC_1 & MC_CGM_MUX_8_DC_1_DE_MASK) >> … in Clock_Ip_Get_ETH1_TX_RGMII_LPBK_CLK_Frequency() 3298 …Frequency /= (((IP_MC_CGM_1->MUX_8_DC_1 & MC_CGM_MUX_8_DC_1_DIV_MASK) >> MC_CGM_MUX_8_DC_1_DIV_SHI… in Clock_Ip_Get_ETH1_TX_RGMII_LPBK_CLK_Frequency()
/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/
D	S32Z2_MC_CGM.h	`151 …__IO uint32_t MUX_8_DC_1; /**< Clock Mux 8 Divider 1 Control Register, offs… member`

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