Searched refs:MUX_7_DC_2 (Results 1 – 2 of 2) sorted by relevance
143 …__IO uint32_t MUX_7_DC_2; /**< Clock Mux 7 Divider 2 Control Register, offs… member
3197 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_7_DC_2 & MC_CGM_MUX_7_DC_2_DE_MASK) >> … in Clock_Ip_Get_ETH0_REF_RMII_CLK_Frequency()3198 …Frequency /= (((IP_MC_CGM_1->MUX_7_DC_2 & MC_CGM_MUX_7_DC_2_DIV_MASK) >> MC_CGM_MUX_7_DC_2_DIV_SHI… in Clock_Ip_Get_ETH0_REF_RMII_CLK_Frequency()