MUX_7_DC_1 (reference) in projects: hal_nxp-3.5.0

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Searched refs:MUX_7_DC_1 (Results 1 – 2 of 2) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/src/
D	Clock_Ip_Frequency.c	1806 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_7_DC_1 & MC_CGM_MUX_7_DC_1_DE_MASK) >> … in Clock_Ip_Get_MSCDSPI_CLK_Frequency() 1807 …Frequency /= (((IP_MC_CGM_0->MUX_7_DC_1 & MC_CGM_MUX_7_DC_1_DIV_MASK) >> MC_CGM_MUX_7_DC_1_DIV_SHI… in Clock_Ip_Get_MSCDSPI_CLK_Frequency() 2966 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_7_DC_1 & MC_CGM_MUX_7_DC_1_DE_MASK) >> … in Clock_Ip_Get_P0_DSPI_MSC_CLK_Frequency() 2967 …Frequency /= (((IP_MC_CGM_0->MUX_7_DC_1 & MC_CGM_MUX_7_DC_1_DIV_MASK) >> MC_CGM_MUX_7_DC_1_DIV_SHI… in Clock_Ip_Get_P0_DSPI_MSC_CLK_Frequency() 3217 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_7_DC_1 & MC_CGM_MUX_7_DC_1_DE_MASK) >> … in Clock_Ip_Get_ETH0_RX_RGMII_CLK_Frequency() 3218 …Frequency /= (((IP_MC_CGM_1->MUX_7_DC_1 & MC_CGM_MUX_7_DC_1_DIV_MASK) >> MC_CGM_MUX_7_DC_1_DIV_SHI… in Clock_Ip_Get_ETH0_RX_RGMII_CLK_Frequency()
/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/
D	S32Z2_MC_CGM.h	`142 …__IO uint32_t MUX_7_DC_1; /**< Clock Mux 7 Divider 1 Control Register, offs… member`

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