Searched refs:MUX_3_DC_3 (Results 1 – 2 of 2) sorted by relevance
3088 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_3_DC_3 & MC_CGM_MUX_3_DC_3_DE_MASK) >> … in Clock_Ip_Get_P0_PSI5_S_TRIG3_CLK_Frequency()3089 …Frequency /= (((IP_MC_CGM_0->MUX_3_DC_3 & MC_CGM_MUX_3_DC_3_DIV_MASK) >> MC_CGM_MUX_3_DC_3_DIV_SHI… in Clock_Ip_Get_P0_PSI5_S_TRIG3_CLK_Frequency()3489 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_3_DC_3 & MC_CGM_MUX_3_DC_3_DE_MASK) >> … in Clock_Ip_Get_P4_PSI5_S_TRIG3_CLK_Frequency()3490 …Frequency /= (((IP_MC_CGM_4->MUX_3_DC_3 & MC_CGM_MUX_3_DC_3_DIV_MASK) >> MC_CGM_MUX_3_DC_3_DIV_SHI… in Clock_Ip_Get_P4_PSI5_S_TRIG3_CLK_Frequency()
114 …__IO uint32_t MUX_3_DC_3; /**< Clock Mux 3 Divider 3 Control Register, offs… member