Searched refs:MUX_2_DC_4 (Results 1 – 2 of 2) sorted by relevance
3098 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_2_DC_4 & MC_CGM_MUX_2_DC_4_DE_MASK) >> … in Clock_Ip_Get_P0_PSI5_S_UART_CLK_Frequency()3099 …Frequency /= (((IP_MC_CGM_0->MUX_2_DC_4 & MC_CGM_MUX_2_DC_4_DIV_MASK) >> MC_CGM_MUX_2_DC_4_DIV_SHI… in Clock_Ip_Get_P0_PSI5_S_UART_CLK_Frequency()3499 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_2_DC_4 & MC_CGM_MUX_2_DC_4_DE_MASK) >> … in Clock_Ip_Get_P4_PSI5_S_UART_CLK_Frequency()3500 …Frequency /= (((IP_MC_CGM_4->MUX_2_DC_4 & MC_CGM_MUX_2_DC_4_DIV_MASK) >> MC_CGM_MUX_2_DC_4_DIV_SHI… in Clock_Ip_Get_P4_PSI5_S_UART_CLK_Frequency()
105 …__IO uint32_t MUX_2_DC_4; /**< Clock Mux 2 Divider 4 Control Register, offs… member