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Searched refs:MUX_2_DC_2 (Results 1 – 4 of 4) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32k3/Mcu/src/
DClock_Ip_Divider.c171 IP_MC_CGM_0->MUX_2_DC_2 &= ~MC_CGM_MUX_2_DC_2_DIV_FMT_MASK; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
175 IP_MC_CGM_4->MUX_2_DC_2 &= ~MC_CGM_MUX_2_DC_2_DIV_FMT_MASK; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Divider.c161 IP_MC_CGM_0->MUX_2_DC_2 &= ~MC_CGM_MUX_2_DC_2_DIV_FMT_MASK; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
165 IP_MC_CGM_4->MUX_2_DC_2 &= ~MC_CGM_MUX_2_DC_2_DIV_FMT_MASK; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
DClock_Ip_Frequency.c3035 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_2_DC_2 & MC_CGM_MUX_2_DC_2_DE_MASK) >> … in Clock_Ip_Get_P0_PSI5_189K_CLK_Frequency()
3036 …Frequency /= (((IP_MC_CGM_0->MUX_2_DC_2 & MC_CGM_MUX_2_DC_2_DIV_MASK) >> MC_CGM_MUX_2_DC_2_DIV_SHI… in Clock_Ip_Get_P0_PSI5_189K_CLK_Frequency()
3425 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_2_DC_2 & MC_CGM_MUX_2_DC_2_DE_MASK) >> … in Clock_Ip_Get_P4_PSI5_189K_CLK_Frequency()
3426 …Frequency /= (((IP_MC_CGM_4->MUX_2_DC_2 & MC_CGM_MUX_2_DC_2_DIV_MASK) >> MC_CGM_MUX_2_DC_2_DIV_SHI… in Clock_Ip_Get_P4_PSI5_189K_CLK_Frequency()
/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_MC_CGM.h103 …__IO uint32_t MUX_2_DC_2; /**< Clock Mux 2 Divider 2 Control Register, offs… member