Searched refs:MUX_1_DC_1 (Results 1 – 2 of 2) sorted by relevance
3152 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_1_DC_1 & MC_CGM_MUX_1_DC_1_DE_MASK) >> … in Clock_Ip_Get_P0_REG_INTF_2X_CLK_Frequency()3153 …Frequency /= (((IP_MC_CGM_0->MUX_1_DC_1 & MC_CGM_MUX_1_DC_1_DIV_MASK) >> MC_CGM_MUX_1_DC_1_DIV_SHI… in Clock_Ip_Get_P0_REG_INTF_2X_CLK_Frequency()3593 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_1_DC_1 & MC_CGM_MUX_1_DC_1_DE_MASK) >> … in Clock_Ip_Get_P4_REG_INTF_2X_CLK_Frequency()3594 …Frequency /= (((IP_MC_CGM_4->MUX_1_DC_1 & MC_CGM_MUX_1_DC_1_DIV_MASK) >> MC_CGM_MUX_1_DC_1_DIV_SHI… in Clock_Ip_Get_P4_REG_INTF_2X_CLK_Frequency()
96 …__IO uint32_t MUX_1_DC_1; /**< Clock Mux 1 Divider 1 Control Register, offs… member