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Searched refs:MUX_1_CSC (Results 1 – 5 of 5) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_RTU_MC_CGM.h90 …__IO uint32_t MUX_1_CSC; /**< Clock Mux 1 Select Control Register, offset:… member
DS32Z2_MC_CGM.h93 …__IO uint32_t MUX_1_CSC; /**< Clock Mux 1 Select Control Register, offset:… member
/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Data.c2617 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_0->MUX_1_CSC),
2636 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_1->MUX_1_CSC),
2655 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_2->MUX_1_CSC),
2674 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_3->MUX_1_CSC),
2692 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_4->MUX_1_CSC),
2710 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_5->MUX_1_CSC),
2728 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_6->MUX_1_CSC),
2746 (Clock_Ip_CgmMuxType*)(&CLOCK_IP_RTU0__MC_CGM->MUX_1_CSC),
2764 (Clock_Ip_CgmMuxType*)(&CLOCK_IP_RTU1__MC_CGM->MUX_1_CSC),
/hal_nxp-3.5.0/s32/drivers/s32k3/BaseNXP/header/
DS32K344_MC_CGM.h92 …__IO uint32_t MUX_1_CSC; /**< Clock Mux 1 Select Control Register, offset:… member
/hal_nxp-3.5.0/s32/drivers/s32k3/Mcu/src/
DClock_Ip_Data.c3316 (Clock_Ip_CgmMuxType*)(&(IP_MC_CGM->MUX_1_CSC)),