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Searched refs:MUX_0_DIV_UPD_STAT (Results 1 – 3 of 3) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_RTU_MC_CGM.h89 …__I uint32_t MUX_0_DIV_UPD_STAT; /**< Clock Mux 0 Divider Update Status Register, … member
DS32Z2_MC_CGM.h92 …__I uint32_t MUX_0_DIV_UPD_STAT; /**< Clock Mux 0 Divider Update Status Register, … member
/hal_nxp-3.5.0/s32/drivers/s32k3/BaseNXP/header/
DS32K344_MC_CGM.h91 …__I uint32_t MUX_0_DIV_UPD_STAT; /**< Clock Mux 0 Divider Update Status Register, … member