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Searched refs:MUX_0_DC_3 (Results 1 – 2 of 2) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32k3/BaseNXP/header/
DS32K344_MC_CGM.h84 …__IO uint32_t MUX_0_DC_3; /**< Clock Mux 0 Divider 3 Control Register, offs… member
/hal_nxp-3.5.0/s32/drivers/s32k3/Mcu/src/
DClock_Ip_Frequency.c1963 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_0_DC_3 & MC_CGM_MUX_0_DC_3_DE_MASK) >> MC… in Clock_Ip_Get_HSE_CLK_Frequency()
1964 …Frequency /= (((IP_MC_CGM->MUX_0_DC_3 & MC_CGM_MUX_0_DC_3_DIV_MASK) >> MC_CGM_MUX_0_DC_3_DIV_SHIFT… in Clock_Ip_Get_HSE_CLK_Frequency()