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Searched refs:MUX_0_DC_1 (Results 1 – 3 of 3) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32k3/BaseNXP/header/
DS32K344_MC_CGM.h82 …__IO uint32_t MUX_0_DC_1; /**< Clock Mux 0 Divider 1 Control Register, offs… member
/hal_nxp-3.5.0/s32/drivers/s32k3/Mcu/src/
DClock_Ip_Frequency.c1949 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_0_DC_1 & MC_CGM_MUX_0_DC_1_DE_MASK) >> MC… in Clock_Ip_Get_AIPS_PLAT_CLK_Frequency()
1950 …Frequency /= (((IP_MC_CGM->MUX_0_DC_1 & MC_CGM_MUX_0_DC_1_DIV_MASK) >> MC_CGM_MUX_0_DC_1_DIV_SHIFT… in Clock_Ip_Get_AIPS_PLAT_CLK_Frequency()
/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_MC_CGM.h90 …__IO uint32_t MUX_0_DC_1; /**< Clock Mux 0 Divider 1 Control Register, offs… member