Searched refs:MUX_0_DC_1 (Results 1 – 3 of 3) sorted by relevance
82 …__IO uint32_t MUX_0_DC_1; /**< Clock Mux 0 Divider 1 Control Register, offs… member
1949 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_0_DC_1 & MC_CGM_MUX_0_DC_1_DE_MASK) >> MC… in Clock_Ip_Get_AIPS_PLAT_CLK_Frequency()1950 …Frequency /= (((IP_MC_CGM->MUX_0_DC_1 & MC_CGM_MUX_0_DC_1_DIV_MASK) >> MC_CGM_MUX_0_DC_1_DIV_SHIFT… in Clock_Ip_Get_AIPS_PLAT_CLK_Frequency()
90 …__IO uint32_t MUX_0_DC_1; /**< Clock Mux 0 Divider 1 Control Register, offs… member