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Searched refs:MIPI_DSI_CSR_ULPS_CTRL (Results 1 – 16 of 16) sorted by relevance

/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX5/drivers/
Dfsl_soc_mipi_dsi.h34 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->ULPS_CTRL) macro
38 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->TX_ULPS_ENABLE) macro
74 MIPI_DSI_CSR_ULPS_CTRL(csr) = MIPI_DSI_CSR_ULPS_CTRL_ULPS_MASK; in SOC_MIPI_DSI_EnableUlps()
78 MIPI_DSI_CSR_ULPS_CTRL(csr) = 0U; in SOC_MIPI_DSI_EnableUlps()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX4/drivers/
Dfsl_soc_mipi_dsi.h34 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->ULPS_CTRL) macro
38 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->TX_ULPS_ENABLE) macro
74 MIPI_DSI_CSR_ULPS_CTRL(csr) = MIPI_DSI_CSR_ULPS_CTRL_ULPS_MASK; in SOC_MIPI_DSI_EnableUlps()
78 MIPI_DSI_CSR_ULPS_CTRL(csr) = 0U; in SOC_MIPI_DSI_EnableUlps()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX3/drivers/
Dfsl_soc_mipi_dsi.h34 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->ULPS_CTRL) macro
38 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->TX_ULPS_ENABLE) macro
74 MIPI_DSI_CSR_ULPS_CTRL(csr) = MIPI_DSI_CSR_ULPS_CTRL_ULPS_MASK; in SOC_MIPI_DSI_EnableUlps()
78 MIPI_DSI_CSR_ULPS_CTRL(csr) = 0U; in SOC_MIPI_DSI_EnableUlps()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8UX5/drivers/
Dfsl_soc_mipi_dsi.h34 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->ULPS_CTRL) macro
38 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->TX_ULPS_ENABLE) macro
74 MIPI_DSI_CSR_ULPS_CTRL(csr) = MIPI_DSI_CSR_ULPS_CTRL_ULPS_MASK; in SOC_MIPI_DSI_EnableUlps()
78 MIPI_DSI_CSR_ULPS_CTRL(csr) = 0U; in SOC_MIPI_DSI_EnableUlps()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX6/drivers/
Dfsl_soc_mipi_dsi.h34 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->ULPS_CTRL) macro
38 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->TX_ULPS_ENABLE) macro
74 MIPI_DSI_CSR_ULPS_CTRL(csr) = MIPI_DSI_CSR_ULPS_CTRL_ULPS_MASK; in SOC_MIPI_DSI_EnableUlps()
78 MIPI_DSI_CSR_ULPS_CTRL(csr) = 0U; in SOC_MIPI_DSI_EnableUlps()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8UX6/drivers/
Dfsl_soc_mipi_dsi.h34 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->ULPS_CTRL) macro
38 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->TX_ULPS_ENABLE) macro
74 MIPI_DSI_CSR_ULPS_CTRL(csr) = MIPI_DSI_CSR_ULPS_CTRL_ULPS_MASK; in SOC_MIPI_DSI_EnableUlps()
78 MIPI_DSI_CSR_ULPS_CTRL(csr) = 0U; in SOC_MIPI_DSI_EnableUlps()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX3/drivers/
Dfsl_soc_mipi_dsi.h34 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->ULPS_CTRL) macro
38 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->TX_ULPS_ENABLE) macro
74 MIPI_DSI_CSR_ULPS_CTRL(csr) = MIPI_DSI_CSR_ULPS_CTRL_ULPS_MASK; in SOC_MIPI_DSI_EnableUlps()
78 MIPI_DSI_CSR_ULPS_CTRL(csr) = 0U; in SOC_MIPI_DSI_EnableUlps()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX2/drivers/
Dfsl_soc_mipi_dsi.h34 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->ULPS_CTRL) macro
38 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->TX_ULPS_ENABLE) macro
74 MIPI_DSI_CSR_ULPS_CTRL(csr) = MIPI_DSI_CSR_ULPS_CTRL_ULPS_MASK; in SOC_MIPI_DSI_EnableUlps()
78 MIPI_DSI_CSR_ULPS_CTRL(csr) = 0U; in SOC_MIPI_DSI_EnableUlps()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QM6/drivers/
Dfsl_soc_mipi_dsi.h34 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->ULPS_CTRL) macro
38 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->TX_ULPS_ENABLE) macro
74 MIPI_DSI_CSR_ULPS_CTRL(csr) = MIPI_DSI_CSR_ULPS_CTRL_ULPS_MASK; in SOC_MIPI_DSI_EnableUlps()
78 MIPI_DSI_CSR_ULPS_CTRL(csr) = 0U; in SOC_MIPI_DSI_EnableUlps()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX5/drivers/
Dfsl_soc_mipi_dsi.h34 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->ULPS_CTRL) macro
38 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->TX_ULPS_ENABLE) macro
74 MIPI_DSI_CSR_ULPS_CTRL(csr) = MIPI_DSI_CSR_ULPS_CTRL_ULPS_MASK; in SOC_MIPI_DSI_EnableUlps()
78 MIPI_DSI_CSR_ULPS_CTRL(csr) = 0U; in SOC_MIPI_DSI_EnableUlps()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX1/drivers/
Dfsl_soc_mipi_dsi.h34 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->ULPS_CTRL) macro
38 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->TX_ULPS_ENABLE) macro
74 MIPI_DSI_CSR_ULPS_CTRL(csr) = MIPI_DSI_CSR_ULPS_CTRL_ULPS_MASK; in SOC_MIPI_DSI_EnableUlps()
78 MIPI_DSI_CSR_ULPS_CTRL(csr) = 0U; in SOC_MIPI_DSI_EnableUlps()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX4/drivers/
Dfsl_soc_mipi_dsi.h34 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->ULPS_CTRL) macro
38 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->TX_ULPS_ENABLE) macro
74 MIPI_DSI_CSR_ULPS_CTRL(csr) = MIPI_DSI_CSR_ULPS_CTRL_ULPS_MASK; in SOC_MIPI_DSI_EnableUlps()
78 MIPI_DSI_CSR_ULPS_CTRL(csr) = 0U; in SOC_MIPI_DSI_EnableUlps()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX1/drivers/
Dfsl_soc_mipi_dsi.h34 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->ULPS_CTRL) macro
38 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->TX_ULPS_ENABLE) macro
74 MIPI_DSI_CSR_ULPS_CTRL(csr) = MIPI_DSI_CSR_ULPS_CTRL_ULPS_MASK; in SOC_MIPI_DSI_EnableUlps()
78 MIPI_DSI_CSR_ULPS_CTRL(csr) = 0U; in SOC_MIPI_DSI_EnableUlps()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX2/drivers/
Dfsl_soc_mipi_dsi.h34 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->ULPS_CTRL) macro
38 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->TX_ULPS_ENABLE) macro
74 MIPI_DSI_CSR_ULPS_CTRL(csr) = MIPI_DSI_CSR_ULPS_CTRL_ULPS_MASK; in SOC_MIPI_DSI_EnableUlps()
78 MIPI_DSI_CSR_ULPS_CTRL(csr) = 0U; in SOC_MIPI_DSI_EnableUlps()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX6/drivers/
Dfsl_soc_mipi_dsi.h34 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->ULPS_CTRL) macro
38 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->TX_ULPS_ENABLE) macro
74 MIPI_DSI_CSR_ULPS_CTRL(csr) = MIPI_DSI_CSR_ULPS_CTRL_ULPS_MASK; in SOC_MIPI_DSI_EnableUlps()
78 MIPI_DSI_CSR_ULPS_CTRL(csr) = 0U; in SOC_MIPI_DSI_EnableUlps()
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/mipi_dsi_split/
Dfsl_mipi_dsi.c77 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->ULPS_CTRL) macro
81 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->TX_ULPS_ENABLE) macro
433 MIPI_DSI_CSR_ULPS_CTRL(csr) = MIPI_DSI_CSR_ULPS_CTRL_ULPS_MASK; in DSI_Init()
437 MIPI_DSI_CSR_ULPS_CTRL(csr) = 0U; in DSI_Init()