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Searched refs:Instance (Results 1 – 25 of 42) sorted by relevance

12

/hal_nxp-3.5.0/s32/drivers/s32k3/Pwm/src/
DEmios_Pwm_Ip.c235 static inline boolean Emios_Pwm_Ip_ValidateMode(uint8 Instance, in Emios_Pwm_Ip_ValidateMode() argument
242 …Ret = (((Emios_Pwm_Ip_aChannelModes[Instance][(uint8)Mode] >> Channel) & 0x01UL) == 1UL) ? TRUE : … in Emios_Pwm_Ip_ValidateMode()
247 (void) Instance; in Emios_Pwm_Ip_ValidateMode()
263 static inline Emios_Pwm_Ip_PeriodType Emios_Pwm_Ip_GetCounterBusPeriod(uint8 Instance, in Emios_Pwm_Ip_GetCounterBusPeriod() argument
268 DevAssert(EMIOS_PWM_IP_INSTANCE_COUNT > Instance); in Emios_Pwm_Ip_GetCounterBusPeriod()
280 ChPeriod = Emios_Mcl_Ip_GetCounterBusPeriod(Instance, MasterBusCh); in Emios_Pwm_Ip_GetCounterBusPeriod()
292 static inline Emios_Pwm_Ip_MasterBusModeType Emios_Pwm_Ip_GetCounterBusMode(uint8 Instance, in Emios_Pwm_Ip_GetCounterBusMode() argument
297 const Emios_Pwm_Ip_HwAddrType *const Base = Emios_Pwm_Ip_aBasePtr[Instance]; in Emios_Pwm_Ip_GetCounterBusMode()
326 static void Emios_Pwm_Ip_InitPeriodDutyCycleOpwfmbMode(uint8 Instance, in Emios_Pwm_Ip_InitPeriodDutyCycleOpwfmbMode() argument
331 DevAssert(EMIOS_PWM_IP_INSTANCE_COUNT > Instance); in Emios_Pwm_Ip_InitPeriodDutyCycleOpwfmbMode()
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DEmios_Pwm_Ip_Irq.c207 static void Emios_Pwm_Ip_IrqDaocHandler(uint8 Instance, uint8 Channel) in Emios_Pwm_Ip_IrqDaocHandler() argument
212 …ax = Emios_Pwm_Ip_GetUCRegA(Emios_Pwm_Ip_aBasePtr[Instance], Emios_Pwm_Ip_GetMasterBusChannel(Inst… in Emios_Pwm_Ip_IrqDaocHandler()
214 …_Ip_PolarityType Polarity = Emios_Pwm_Ip_GetEdgePolarity(Emios_Pwm_Ip_aBasePtr[Instance], Channel); in Emios_Pwm_Ip_IrqDaocHandler()
215 boolean OutputPin = Emios_Pwm_Ip_GetOutputPinState(Emios_Pwm_Ip_aBasePtr[Instance], Channel); in Emios_Pwm_Ip_IrqDaocHandler()
217 …WM_IP_MODE_DAOC_FLAG == Emios_Pwm_Ip_aCurrentModes[eMios_Pwm_Ip_IndexInChState[Instance][Channel]]) in Emios_Pwm_Ip_IrqDaocHandler()
219 …Period[eMios_Pwm_Ip_IndexInChState[Instance][Channel]] - Emios_Pwm_Ip_aDutyCycle[eMios_Pwm_Ip_Inde… in Emios_Pwm_Ip_IrqDaocHandler()
220 …DaocRegA = ((DaocDuty + Emios_Pwm_Ip_GetUCRegB(Emios_Pwm_Ip_aBasePtr[Instance], Channel)) % Counte… in Emios_Pwm_Ip_IrqDaocHandler()
222 …Emios_Pwm_Ip_SetUCRegA(Emios_Pwm_Ip_aBasePtr[Instance], Channel, (DaocRegA == 0U)? CounterMax : Da… in Emios_Pwm_Ip_IrqDaocHandler()
224 …Ip_aPeriod[eMios_Pwm_Ip_IndexInChState[Instance][Channel]] + Emios_Pwm_Ip_GetUCRegB(Emios_Pwm_Ip_a… in Emios_Pwm_Ip_IrqDaocHandler()
225 …Emios_Pwm_Ip_SetUCRegB(Emios_Pwm_Ip_aBasePtr[Instance], Channel, (DaocRegB == 0U)? CounterMax : Da… in Emios_Pwm_Ip_IrqDaocHandler()
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/hal_nxp-3.5.0/s32/drivers/s32k3/Eth_GMAC/include/
DGmac_Ip.h113 Gmac_Ip_StatusType Gmac_Ip_Init(uint8 Instance,
123 void Gmac_Ip_Deinit(uint8 Instance);
131 Gmac_Ip_PowerStateType Gmac_Ip_GetPowerState(uint8 Instance);
139 void Gmac_Ip_SetPowerState(uint8 Instance, Gmac_Ip_PowerStateType PowerState);
146 void Gmac_Ip_EnableController(uint8 Instance);
158 Gmac_Ip_StatusType Gmac_Ip_DisableController(uint8 Instance);
166 void Gmac_Ip_SetSpeed(uint8 Instance, Gmac_Ip_SpeedType Speed);
191 Gmac_Ip_StatusType Gmac_Ip_GetTxBuff(uint8 Instance,
217 Gmac_Ip_StatusType Gmac_Ip_SendFrame(uint8 Instance,
244 Gmac_Ip_StatusType Gmac_Ip_SendMultiBufferFrame(uint8 Instance,
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/hal_nxp-3.5.0/s32/drivers/s32k3/Eth_GMAC/src/
DGmac_Ip.c270 static Gmac_Ip_StatusType Gmac_Ip_InitDMA(uint8 Instance,
272 static void Gmac_Ip_InitStateStructure(uint8 Instance,
274 static void Gmac_Ip_InitTxBD(uint8 Instance,
278 static void Gmac_Ip_InitRxBD(uint8 Instance,
289 uint8 Instance,
295 static void Gmac_Ip_InitMTL(uint8 Instance, const Gmac_CtrlConfigType *Config);
306 static void Gmac_Ip_RestoreTxDescr(uint8 Instance);
308 static void Gmac_Ip_RestoreRxDescr(uint8 Instance);
311 uint8 Instance,
318 static void Gmac_Ip_ReadTimeStampInfo(uint8 Instance,
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DGmac_Ip_Hw_Access.c128 const uint8 Instance, \
133 const uint8 Instance, \
138 const uint8 Instance, \
178 const uint8 Instance, \ in GMAC_IrqFSMHandler() argument
185 Gmac_apxState[Instance]->SafetyCallback(Instance, GMAC_SAF_ERR_FSM_STATE_PARITY); in GMAC_IrqFSMHandler()
189 Gmac_apxState[Instance]->SafetyCallback(Instance, GMAC_SAF_ERR_FSM_TIMEOUT); in GMAC_IrqFSMHandler()
193 Gmac_apxState[Instance]->SafetyCallback(Instance, GMAC_SAF_ERR_MASTER_INTERFACE_TIMEOUT); in GMAC_IrqFSMHandler()
197 Gmac_apxState[Instance]->SafetyCallback(Instance, GMAC_SAF_ERR_CSR_EMPTY_DATA); in GMAC_IrqFSMHandler()
206 const uint8 Instance, \ in GMAC_IrqFSMDPPHandler() argument
211 const GMAC_Type *Base = Gmac_apxBases[Instance]; in GMAC_IrqFSMDPPHandler()
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/hal_nxp-3.5.0/s32/drivers/s32ze/Uart/src/
DLinflexd_Uart_Ip.c213 static Linflexd_Uart_Ip_StatusType Linflexd_Uart_Ip_StartSendUsingInterrupts(const uint8 Instance,
216 …atic Linflexd_Uart_Ip_StatusType Linflexd_Uart_Ip_StartReceiveUsingInterrupts(const uint8 Instance,
219 static void Linflexd_Uart_Ip_CompleteSendUsingInterrupts(const uint8 Instance);
220 static void Linflexd_Uart_Ip_CompleteReceiveUsingInterrupts(const uint8 Instance);
222 static Linflexd_Uart_Ip_StatusType Linflexd_Uart_Ip_StartSendUsingDma(const uint8 Instance,
225 static Linflexd_Uart_Ip_StatusType Linflexd_Uart_Ip_StartReceiveUsingDma(const uint8 Instance,
230 static void Linflexd_Uart_Ip_PutData(const uint8 Instance);
231 static void Linflexd_Uart_Ip_GetData(const uint8 Instance);
232 static void Linflexd_Uart_Ip_SetWordLength(const uint8 Instance);
233 static void Linflexd_Uart_Ip_SetUp_Init(const uint8 Instance);
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/hal_nxp-3.5.0/s32/drivers/s32k3/Pwm/include/
DEmios_Pwm_Ip.h126 void Emios_Pwm_Ip_InitChannel(uint8 Instance,
136 void Emios_Pwm_Ip_DeInitChannel(uint8 Instance,
148 void Emios_Pwm_Ip_ForceMatchLeadingEdge(uint8 Instance,
161 void Emios_Pwm_Ip_ForceMatchTrailingEdge(uint8 Instance,
173 Emios_Pwm_Ip_PeriodType Emios_Pwm_Ip_GetPeriod(uint8 Instance,
184 void Emios_Pwm_Ip_SetPeriod(uint8 Instance,
195 Emios_Pwm_Ip_DutyType Emios_Pwm_Ip_GetDutyCycle(uint8 Instance,
208 Emios_Pwm_Ip_StatusType Emios_Pwm_Ip_SetDutyCycle(uint8 Instance,
219 Emios_Pwm_Ip_PeriodType Emios_Pwm_Ip_GetPhaseShift(uint8 Instance,
230 Emios_Pwm_Ip_StatusType Emios_Pwm_Ip_SetPhaseShift(uint8 Instance,
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/hal_nxp-3.5.0/s32/drivers/s32k3/Mcu/src/
DClock_Ip_Pll.c163 uint32 Instance; in Clock_Ip_ResetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize() local
168 Instance = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_MODULE_INSTANCE]; in Clock_Ip_ResetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
171 for (DividerIndex = 0U; DividerIndex < Clock_Ip_apxPll[Instance].DivsNo; DividerIndex++) in Clock_Ip_ResetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
173 Clock_Ip_apxPll[Instance].PllInstance->PLLODIV[DividerIndex] &= ~PLL_PLLODIV_DE_MASK; in Clock_Ip_ResetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
176 Clock_Ip_apxPll[Instance].PllInstance->PLLCR |= PLL_PLLCR_PLLPD_MASK; in Clock_Ip_ResetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
180 (void)Instance; in Clock_Ip_ResetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
186 uint32 Instance; in Clock_Ip_SetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize() local
191 Instance = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_MODULE_INSTANCE]; in Clock_Ip_SetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
196 Value = Clock_Ip_apxPll[Instance].PllInstance->PLLDV; in Clock_Ip_SetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
200 Clock_Ip_apxPll[Instance].PllInstance->PLLDV = Value; in Clock_Ip_SetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
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DClock_Ip_ExtOsc.c157 uint32 Instance; in Clock_Ip_ResetFxoscOsconBypEocvGmSel() local
161 Instance = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_MODULE_INSTANCE]; in Clock_Ip_ResetFxoscOsconBypEocvGmSel()
164 Clock_Ip_apxXosc[Instance]->CTRL &= ~FXOSC_CTRL_OSCON_MASK; in Clock_Ip_ResetFxoscOsconBypEocvGmSel()
168 (void)Instance; in Clock_Ip_ResetFxoscOsconBypEocvGmSel()
175 uint32 Instance; in Clock_Ip_SetFxoscOsconBypEocvGmSel() local
179 Instance = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_MODULE_INSTANCE]; in Clock_Ip_SetFxoscOsconBypEocvGmSel()
183 Clock_Ip_apxXosc[Instance]->CTRL = in Clock_Ip_SetFxoscOsconBypEocvGmSel()
209 (void)Instance; in Clock_Ip_SetFxoscOsconBypEocvGmSel()
219 uint32 Instance; in Clock_Ip_CompleteFxoscOsconBypEocvGmSel() local
223 Instance = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_MODULE_INSTANCE]; in Clock_Ip_CompleteFxoscOsconBypEocvGmSel()
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DClock_Ip_Selector.c150 uint32 Instance; in Clock_Ip_ResetCgmXCscCssClkswSwip() local
156 Instance = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_MODULE_INSTANCE]; in Clock_Ip_ResetCgmXCscCssClkswSwip()
160 Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC |= MC_CGM_MUX_CSC_SAFE_SW_MASK; in Clock_Ip_ResetCgmXCscCssClkswSwip()
161 Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC &= ~SelectorMask; in Clock_Ip_ResetCgmXCscCssClkswSwip()
165 (void)Instance; in Clock_Ip_ResetCgmXCscCssClkswSwip()
175 uint32 Instance; in Clock_Ip_SetCgmXCscCssClkswSwip() local
190 Instance = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_MODULE_INSTANCE]; in Clock_Ip_SetCgmXCscCssClkswSwip()
198 …if (SelectorValue != ((Clock_Ip_apxCgm[Instance][SelectorIndex]->CSS & SelectorMask) >> SelectorSh… in Clock_Ip_SetCgmXCscCssClkswSwip()
205 …while((MC_CGM_MUX_CSS_SWIP_IN_PROGRESS == (Clock_Ip_apxCgm[Instance][SelectorIndex]->CSS & MC_CGM_… in Clock_Ip_SetCgmXCscCssClkswSwip()
209 RegValue = Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC; in Clock_Ip_SetCgmXCscCssClkswSwip()
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DClock_Ip_Divider.c138 uint32 Instance; in Clock_Ip_SetCgmXDeDivStatWithoutPhase() local
154 Instance = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_MODULE_INSTANCE]; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
163 RegValue = Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex]; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
166 Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex] = RegValue; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
169 if((Instance == 0U) && (SelectorIndex == 2U) && (DividerIndex == 2U)) in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
173 else if((Instance == 4U) && (SelectorIndex == 2U) && (DividerIndex == 2U)) in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
188 …DividerStatus = (Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_UPD_STAT & MC_CGM_MUX_DIV_UPD_S… in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
199 … Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex] |= MC_CGM_MUX_DC_DE_MASK; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
203 … Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex] &= ~MC_CGM_MUX_DC_DE_MASK; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
214 (void)Instance; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
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DClock_Ip_DividerTrigger.c127 uint32 Instance; in Clock_Ip_ConfigureCgmXDivTrigCtrlTctlHhenUpdStat() local
132 Instance = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_MODULE_INSTANCE]; in Clock_Ip_ConfigureCgmXDivTrigCtrlTctlHhenUpdStat()
138 …Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_TRIG_CTRL = (MC_CGM_MUX_DIV_TRIG_CTRL_TCTL_MASK); in Clock_Ip_ConfigureCgmXDivTrigCtrlTctlHhenUpdStat()
142 …Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_TRIG_CTRL &= ~(MC_CGM_MUX_DIV_TRIG_CTRL_TCTL_MAS… in Clock_Ip_ConfigureCgmXDivTrigCtrlTctlHhenUpdStat()
148 (void)Instance; in Clock_Ip_ConfigureCgmXDivTrigCtrlTctlHhenUpdStat()
155 uint32 Instance; in Clock_Ip_TriggerUpdateCgmXDivTrigCtrlTctlHhenUpdStat() local
166 Instance = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_MODULE_INSTANCE]; in Clock_Ip_TriggerUpdateCgmXDivTrigCtrlTctlHhenUpdStat()
172 …Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_TRIG = MC_CGM_MUX_DIV_TRIG_TRIGGER(CLOCK_IP_TRIG… in Clock_Ip_TriggerUpdateCgmXDivTrigCtrlTctlHhenUpdStat()
178 …DividerStatus = (Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_UPD_STAT & MC_CGM_MUX_DIV_UPD_S… in Clock_Ip_TriggerUpdateCgmXDivTrigCtrlTctlHhenUpdStat()
193 (void)Instance; in Clock_Ip_TriggerUpdateCgmXDivTrigCtrlTctlHhenUpdStat()
/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Pll.c170 uint32 Instance = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_MODULE_INSTANCE]; in Clock_Ip_ResetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize() local
174 for (DividerIndex = 0U; DividerIndex < Clock_Ip_apxPll[Instance].DivsNo; DividerIndex++) in Clock_Ip_ResetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
176 Clock_Ip_apxPll[Instance].PllInstance->PLLODIV[DividerIndex] &= ~PLLDIG_PLLODIV_DE_MASK; in Clock_Ip_ResetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
180 Clock_Ip_apxPll[Instance].PllInstance->PLLCR |= PLLDIG_PLLCR_PLLPD_MASK; in Clock_Ip_ResetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
184 uint32 Instance = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_MODULE_INSTANCE]; in Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize() local
194 …Clock_Ip_apxPll[Instance].PllInstance->PLLCLKMUX = PLLDIG_PLLCLKMUX_REFCLKSEL(CLOCK_IP_FIRC_PLL_RE… in Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
198 …Clock_Ip_apxPll[Instance].PllInstance->PLLCLKMUX = PLLDIG_PLLCLKMUX_REFCLKSEL(CLOCK_IP_FXOSC_PLL_R… in Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
208 Clock_Ip_apxPll[Instance].PllInstance->PLLDV = Value; in Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
210 Value = Clock_Ip_apxPll[Instance].PllInstance->PLLFD; in Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
214 Clock_Ip_apxPll[Instance].PllInstance->PLLFD = Value; in Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
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DClock_Ip_Divider.c136 uint32 Instance = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_MODULE_INSTANCE]; in Clock_Ip_SetCgmXDeDivStatWithoutPhase() local
153 RegValue = Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex]; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
156 Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex] = RegValue; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
159 if((Instance == 0U) && (SelectorIndex == 2U) && (DividerIndex == 2U)) in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
163 else if((Instance == 4U) && (SelectorIndex == 2U) && (DividerIndex == 2U)) in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
178 …DividerStatus = (Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_UPD_STAT & MC_CGM_MUX_DIV_UPD_S… in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
189 … Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex] |= MC_CGM_MUX_DC_DE_MASK; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
193 … Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex] &= ~MC_CGM_MUX_DC_DE_MASK; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
207 uint32 Instance = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_MODULE_INSTANCE]; in Clock_Ip_SetCgmXDeDivStatWithoutPhaseWithTrigger() local
224 RegValue = Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex]; in Clock_Ip_SetCgmXDeDivStatWithoutPhaseWithTrigger()
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DClock_Ip_Selector.c152 uint32 Instance = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_MODULE_INSTANCE]; in Clock_Ip_ResetCgmXCscCssClkswSwip() local
157 Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC |= MC_CGM_MUX_CSC_SAFE_SW_MASK; in Clock_Ip_ResetCgmXCscCssClkswSwip()
158 Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC &= ~SelectorMask; in Clock_Ip_ResetCgmXCscCssClkswSwip()
165 uint32 Instance = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_MODULE_INSTANCE]; in Clock_Ip_SetCgmXCscCssClkswSwip() local
179 …if (SelectorValue != ((Clock_Ip_apxCgm[Instance][SelectorIndex]->CSS & SelectorMask) >> SelectorSh… in Clock_Ip_SetCgmXCscCssClkswSwip()
186 …while((MC_CGM_MUX_CSS_SWIP_IN_PROGRESS == (Clock_Ip_apxCgm[Instance][SelectorIndex]->CSS & MC_CGM_… in Clock_Ip_SetCgmXCscCssClkswSwip()
190 RegValue = Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC; in Clock_Ip_SetCgmXCscCssClkswSwip()
194 Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC = RegValue; in Clock_Ip_SetCgmXCscCssClkswSwip()
202 …while((CLOCK_IP_MC_CGM_MUX_CSS_CLK_SW_NOT_REQUESTED == (Clock_Ip_apxCgm[Instance][SelectorIndex]->… in Clock_Ip_SetCgmXCscCssClkswSwip()
212 …while((MC_CGM_MUX_CSS_SWIP_IN_PROGRESS == (Clock_Ip_apxCgm[Instance][SelectorIndex]->CSS & MC_CGM_… in Clock_Ip_SetCgmXCscCssClkswSwip()
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DClock_Ip_ExtOsc.c150 uint32 Instance = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_MODULE_INSTANCE]; in Clock_Ip_ResetFxoscOsconBypEocvGmSel() local
153 Clock_Ip_apxXosc[Instance]->CTRL &= ~FXOSC_CTRL_OSCON_MASK; in Clock_Ip_ResetFxoscOsconBypEocvGmSel()
159 uint32 Instance = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_MODULE_INSTANCE]; in Clock_Ip_SetFxoscOsconBypEocvGmSel() local
163 Clock_Ip_apxXosc[Instance]->CTRL = in Clock_Ip_SetFxoscOsconBypEocvGmSel()
185 uint32 Instance = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_MODULE_INSTANCE]; in Clock_Ip_CompleteFxoscOsconBypEocvGmSel() local
201 …FxoscStatus = ((Clock_Ip_apxXosc[Instance]->STAT & FXOSC_STAT_OSC_STAT_MASK) >> FXOSC_STAT_OSC_STA… in Clock_Ip_CompleteFxoscOsconBypEocvGmSel()
223 uint32 Instance = Clock_Ip_au8ClockFeatures[XoscName][CLOCK_IP_MODULE_INSTANCE]; in Clock_Ip_DisableFxoscOsconBypEocvGmSel() local
226 Clock_Ip_apxXosc[Instance]->CTRL &= ~FXOSC_CTRL_OSCON_MASK; in Clock_Ip_DisableFxoscOsconBypEocvGmSel()
230 uint32 Instance = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_MODULE_INSTANCE]; in Clock_Ip_EnableFxoscOsconBypEocvGmSel() local
235 Clock_Ip_apxXosc[Instance]->CTRL |= FXOSC_CTRL_OSCON_MASK; in Clock_Ip_EnableFxoscOsconBypEocvGmSel()
/hal_nxp-3.5.0/s32/drivers/s32k3/Mcl/src/
DEmios_Mcl_Ip.c161 Emios_Ip_CommonStatusType Emios_Mcl_Ip_Init(uint8 Instance, const Emios_Mcl_Ip_ConfigType* const Co… in Emios_Mcl_Ip_Init() argument
164 DevAssert(Instance < eMIOS_INSTANCE_COUNT); in Emios_Mcl_Ip_Init()
169 eMIOS_Type* Base = Emios_Ip_paxBase[Instance]; in Emios_Mcl_Ip_Init()
178 if (Emios_Ip_axIpIsInitialized[Instance].instanceInitState == TRUE) in Emios_Mcl_Ip_Init()
232 …Emios_Ip_axChState[Instance][(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].counterMode … in Emios_Mcl_Ip_Init()
233 …Emios_Ip_axChState[Instance][(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].channelInitS… in Emios_Mcl_Ip_Init()
236 …Emios_Ip_ChPeriodMasterBus[Instance][(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel] = (u… in Emios_Mcl_Ip_Init()
238 …Emios_Ip_ChPeriodMasterBus[Instance][(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel] = (u… in Emios_Mcl_Ip_Init()
243 Emios_Ip_axIpIsInitialized[Instance].instanceInitState = TRUE; in Emios_Mcl_Ip_Init()
245 Emios_Ip_axIpIsInitialized[Instance].runCore = ConfigPtr->instanceCoreNumber; in Emios_Mcl_Ip_Init()
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/hal_nxp-3.5.0/s32/drivers/s32ze/Spi/src/
DSpi_Ip.c209 static void Spi_Ip_TransferProcess(uint8 Instance);
211 static void Spi_Ip_DmaConfig(uint8 Instance);
212 static void Spi_Ip_CmdDmaTcdSGInit(uint8 Instance);
213 static void Spi_Ip_CmdDmaTcdSGConfig( uint8 Instance,
219 static void Spi_Ip_DmaContinueTransfer(uint8 Instance);
221 static void Spi_Ip_DmaFastConfig(uint8 Instance, const Spi_Ip_FastTransferType *FastTransferCfg, ui…
222 static void Spi_Ip_RxDmaTcdSGConfig(uint8 Instance, uint8 TCDSGIndex, uint8 DisHwReq);
223 static void Spi_Ip_RxDmaTcdSGInit(uint8 Instance);
224 static void Spi_Ip_TxDmaTcdSGConfig(uint8 Instance, uint8 TCDSGIndex, uint8 DisHwReq);
225 static void Spi_Ip_TxDmaTcdSGInit(uint8 Instance);
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/hal_nxp-3.5.0/s32/drivers/s32ze/Uart/include/
DLinflexd_Uart_Ip.h117 Linflexd_Uart_Ip_StatusType Linflexd_Uart_Ip_SetBaudrate(const uint8 Instance,
132 void Linflexd_Uart_Ip_GetBaudrate(const uint8 Instance, uint32 * ConfiguredBaudRate);
143 void Linflexd_Uart_Ip_Init(const uint8 Instance, const Linflexd_Uart_Ip_UserConfigType * UserConfig…
154 Linflexd_Uart_Ip_StatusType Linflexd_Uart_Ip_Deinit(const uint8 Instance);
167 void Linflexd_Uart_Ip_SetTxBuffer(const uint8 Instance,
183 void Linflexd_Uart_Ip_SetRxBuffer(const uint8 Instance,
196 Linflexd_Uart_Ip_StatusType Linflexd_Uart_Ip_AbortReceivingData(const uint8 Instance);
207 Linflexd_Uart_Ip_StatusType Linflexd_Uart_Ip_AbortSendingData(const uint8 Instance);
225 Linflexd_Uart_Ip_StatusType Linflexd_Uart_Ip_SyncSend(const uint8 Instance,
245 Linflexd_Uart_Ip_StatusType Linflexd_Uart_Ip_SyncReceive(const uint8 Instance,
[all …]
/hal_nxp-3.5.0/s32/drivers/s32ze/Swt/src/
DSwt_Ip.c427 Swt_Ip_StatusType Swt_Ip_Init(const uint32 Instance, in Swt_Ip_Init() argument
430 SWT_Type * const Base = Swt_Ip_sBase[Instance]; in Swt_Ip_Init()
434 DevAssert(Instance < SWT_INSTANCE_COUNT); in Swt_Ip_Init()
462 Swt_Ip_apCallbackPtr[Instance] = ConfigPtr->pfSwtCallback; in Swt_Ip_Init()
472 Wdg_Ip_abStatus[Instance] = TRUE; in Swt_Ip_Init()
485 Swt_Ip_StatusType Swt_Ip_Deinit(const uint32 Instance) in Swt_Ip_Deinit() argument
487 SWT_Type * const Base = Swt_Ip_sBase[Instance]; in Swt_Ip_Deinit()
491 DevAssert(Instance < SWT_INSTANCE_COUNT); in Swt_Ip_Deinit()
520 Wdg_Ip_abStatus[Instance] = FALSE; in Swt_Ip_Deinit()
532 void Swt_Ip_Service(const uint32 Instance) in Swt_Ip_Service() argument
[all …]
/hal_nxp-3.5.0/s32/drivers/s32k3/Adc/include/
DAdc_Sar_Ip_HwAccess.h116 static inline void Adc_Sar_Powerup(const uint32 Instance) in Adc_Sar_Powerup() argument
124 if (Instance >= ADC_INSTANCE_COUNT) in Adc_Sar_Powerup()
126 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[Instance - ADC_INSTANCE_COUNT]; in Adc_Sar_Powerup()
132 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[Instance]; in Adc_Sar_Powerup()
143 static inline void Adc_Sar_Powerdown(const uint32 Instance) in Adc_Sar_Powerdown() argument
151 if (Instance >= ADC_INSTANCE_COUNT) in Adc_Sar_Powerdown()
153 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[Instance - ADC_INSTANCE_COUNT]; in Adc_Sar_Powerdown()
159 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[Instance]; in Adc_Sar_Powerdown()
187 static inline void Adc_Sar_WriteThresholds(const uint32 Instance, in Adc_Sar_WriteThresholds() argument
222 if (Instance >= ADC_INSTANCE_COUNT) in Adc_Sar_WriteThresholds()
[all …]
/hal_nxp-3.5.0/s32/drivers/s32k3/Adc/src/
DAdc_Sar_Ip.c292 static inline uint8 Adc_Sar_GetResolution(const uint32 Instance);
295 static inline uint16 Adc_Sar_GetMaskedResult(const uint32 Instance,
297 static inline uint32 Adc_Sar_GetMsrFlags(const uint32 Instance);
298 static inline uint32 Adc_Sar_GetIsrFlags(const uint32 Instance);
302 static inline uint32 Adc_Sar_CollectMcrMasks(const uint32 Instance,
305 static inline void Adc_Sar_ConfigChannels(const uint32 Instance,
309 static inline Adc_Sar_Ip_StatusType Adc_Sar_CheckSelfTestProgress(const uint32 Instance);
310 static inline void Adc_Sar_ConfigSelftestThreshold(const uint32 Instance,
312 static inline void Adc_Sar_EnableSelftestThreshold(const uint32 Instance);
313 static inline void Adc_Sar_DisableSelftestThreshold(const uint32 Instance);
[all …]
/hal_nxp-3.5.0/s32/drivers/s32k3/Mcl/include/
DEmios_Mcl_Ip.h128 void Emios_Mcl_Ip_EnableChannel(uint8 Instance, uint8 HwChannel);
137 void Emios_Mcl_Ip_DisableChannel(uint8 Instance, uint8 HwChannel);
152 void Emios_Mcl_Ip_ComparatorTransferEnable(uint8 Instance, uint32 ChannelMask);
167 void Emios_Mcl_Ip_ComparatorTransferDisable(uint8 Instance, uint32 ChannelMask);
176 Emios_Ip_CommonStatusType Emios_Mcl_Ip_Deinit(uint8 Instance);
186 Emios_Ip_CommonStatusType Emios_Mcl_Ip_Init(uint8 Instance, const Emios_Mcl_Ip_ConfigType *const Co…
234 uint32 Emios_Mcl_Ip_GetCounterBusPeriod(uint8 Instance, uint8 Channel);
236 uint16 Emios_Mcl_Ip_GetCounterBusPeriod(uint8 Instance, uint8 Channel);
257 void Emios_Mcl_Ip_ConfigureGlobalTimebase(uint8 Instance, uint8 Value);
/hal_nxp-3.5.0/s32/drivers/s32ze/Swt/include/
DSwt_Ip.h129 Swt_Ip_StatusType Swt_Ip_Init(const uint32 Instance,
141 Swt_Ip_StatusType Swt_Ip_Deinit(const uint32 Instance);
153 void Swt_Ip_Service(const uint32 Instance);
166 Swt_Ip_StatusType Swt_Ip_Config(const uint32 Instance,
179 Swt_Ip_StatusType Swt_Ip_SetTimeout(const uint32 Instance,
190 Swt_Ip_StatusType Swt_Ip_StartTimer(const uint32 Instance);
200 Swt_Ip_StatusType Swt_Ip_StopTimer(const uint32 Instance);
215 Swt_Ip_StatusType Swt_Ip_ClearResetRequest(const uint32 Instance);
/hal_nxp-3.5.0/s32/drivers/s32ze/Spi/include/
DSpi_Ip.h126 Spi_Ip_StatusType Spi_Ip_DeInit(uint8 Instance);
267 Spi_Ip_HwStatusType Spi_Ip_GetStatus(uint8 Instance);
279 void Spi_Ip_ManageBuffers(uint8 Instance);
331 Spi_Ip_StatusType Spi_Ip_UpdateTransferMode(uint8 Instance, Spi_Ip_ModeType Mode);
342 void Spi_Ip_Cancel(uint8 Instance);
356 Spi_Ip_StatusType Spi_Ip_SetClockMode(uint8 Instance, Spi_Ip_DualClockModeType ClockMode);
359 void Spi_Ip_IrqHandler(uint8 Instance);
361 void Spi_Ip_IrqDmaHandler(uint8 Instance);

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