Searched refs:IP_PLL (Results 1 – 3 of 3) sorted by relevance
94 #define IP_PLL ((PLL_Type *)IP_PLL_BASE) macro98 #define IP_PLL_BASE_PTRS { IP_PLL }
1796 uint32 PLLDVBuffer = IP_PLL->PLLDV; in Clock_Ip_Get_PLL_CLK_Frequency()1797 uint32 PLLFDBuffer = IP_PLL->PLLFD; in Clock_Ip_Get_PLL_CLK_Frequency()1802 Clock_Ip_u32PLL_CLKFreq = Clock_Ip_PLL_VCO(IP_PLL); in Clock_Ip_Get_PLL_CLK_Frequency()1804 …return (((IP_PLL->PLLSR & PLL_PLLSR_LOCK_MASK) >> PLL_PLLSR_LOCK_SHIFT) != 0U) ? Clock_Ip_u32PLL_C… in Clock_Ip_Get_PLL_CLK_Frequency()1820 uint32 DividerValue = (IP_PLL->PLLDV & PLL_PLLDV_ODIV2_MASK) >> PLL_PLLDV_ODIV2_SHIFT; in Clock_Ip_Get_PLL_POSTDIV_CLK_Frequency()1850 …Frequency &= Clock_Ip_au32EnableDivider[((IP_PLL->PLLODIV[0U] & PLL_PLLODIV_DE_MASK) >> PLL_PLLODI… in Clock_Ip_Get_PLL_PHI0_Frequency()1851 …Frequency /= (((IP_PLL->PLLODIV[0U] & PLL_PLLODIV_DIV_MASK) >> PLL_PLLODIV_DIV_SHIFT) + 1U); … in Clock_Ip_Get_PLL_PHI0_Frequency()1857 …Frequency &= Clock_Ip_au32EnableDivider[((IP_PLL->PLLODIV[1U] & PLL_PLLODIV_DE_MASK) >> PLL_PLLODI… in Clock_Ip_Get_PLL_PHI1_Frequency()1858 …Frequency /= (((IP_PLL->PLLODIV[1U] & PLL_PLLODIV_DIV_MASK) >> PLL_PLLODIV_DIV_SHIFT) + 1U); … in Clock_Ip_Get_PLL_PHI1_Frequency()
3410 IP_PLL,
