Home
last modified time | relevance | path

Searched refs:IP_MC_CGM_5 (Results 1 – 3 of 3) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Frequency.c1774 …Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_5->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK)… in Clock_Ip_Get_LIN9_CLK_Frequency()
1775 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_5->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DE_MASK) >> … in Clock_Ip_Get_LIN9_CLK_Frequency()
1776 …Frequency /= (((IP_MC_CGM_5->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DIV_MASK) >> MC_CGM_MUX_2_DC_0_DIV_SHI… in Clock_Ip_Get_LIN9_CLK_Frequency()
1784 …Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_5->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK)… in Clock_Ip_Get_LIN10_CLK_Frequency()
1785 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_5->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DE_MASK) >> … in Clock_Ip_Get_LIN10_CLK_Frequency()
1786 …Frequency /= (((IP_MC_CGM_5->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DIV_MASK) >> MC_CGM_MUX_2_DC_0_DIV_SHI… in Clock_Ip_Get_LIN10_CLK_Frequency()
1794 …Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_5->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK)… in Clock_Ip_Get_LIN11_CLK_Frequency()
1795 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_5->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DE_MASK) >> … in Clock_Ip_Get_LIN11_CLK_Frequency()
1796 …Frequency /= (((IP_MC_CGM_5->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DIV_MASK) >> MC_CGM_MUX_2_DC_0_DIV_SHI… in Clock_Ip_Get_LIN11_CLK_Frequency()
1835 …Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_5->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK)… in Clock_Ip_Get_P5_LIN_BAUD_CLK_Frequency()
[all …]
DClock_Ip_Data.c2709 { (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_5->MUX_0_CSC),
2710 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_5->MUX_1_CSC),
2711 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_5->MUX_2_CSC),
2712 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_5->MUX_3_CSC),
2713 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_5->MUX_4_CSC),
2714 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_5->MUX_5_CSC),
2806 (volatile Clock_Ip_CgmPcfsType*)(&(IP_MC_CGM_5->PCFS_SDUR)),
/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_MC_CGM.h213 #define IP_MC_CGM_5 ((MC_CGM_Type *)IP_MC_CGM_5_BASE) macro
221 … { IP_MC_CGM_0, IP_MC_CGM_1, IP_MC_CGM_2, IP_MC_CGM_3, IP_MC_CGM_4, IP_MC_CGM_5, IP_MC_CGM_6 }