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Searched refs:IP_MC_CGM_0 (Results 1 – 5 of 5) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Frequency.c1655 …Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_6_CSS & MC_CGM_MUX_6_CSS_SELSTAT_MASK)… in Clock_Ip_Get_P0_FR_PE_CLK_Frequency()
1656 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DE_MASK) >> … in Clock_Ip_Get_P0_FR_PE_CLK_Frequency()
1657 …Frequency /= (((IP_MC_CGM_0->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DIV_MASK) >> MC_CGM_MUX_6_DC_0_DIV_SHI… in Clock_Ip_Get_P0_FR_PE_CLK_Frequency()
1664 …Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_6_CSS & MC_CGM_MUX_6_CSS_SELSTAT_MASK)… in Clock_Ip_Get_FRAY0_CLK_Frequency()
1665 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DE_MASK) >> … in Clock_Ip_Get_FRAY0_CLK_Frequency()
1666 …Frequency /= (((IP_MC_CGM_0->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DIV_MASK) >> MC_CGM_MUX_6_DC_0_DIV_SHI… in Clock_Ip_Get_FRAY0_CLK_Frequency()
1674 …Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_6_CSS & MC_CGM_MUX_6_CSS_SELSTAT_MASK)… in Clock_Ip_Get_FRAY1_CLK_Frequency()
1675 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DE_MASK) >> … in Clock_Ip_Get_FRAY1_CLK_Frequency()
1676 …Frequency /= (((IP_MC_CGM_0->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DIV_MASK) >> MC_CGM_MUX_6_DC_0_DIV_SHI… in Clock_Ip_Get_FRAY1_CLK_Frequency()
1685 …Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_7_CSS & MC_CGM_MUX_7_CSS_SELSTAT_MASK)… in Clock_Ip_Get_GTM_CLK_Frequency()
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DClock_Ip_Divider.c161 IP_MC_CGM_0->MUX_2_DC_2 &= ~MC_CGM_MUX_2_DC_2_DIV_FMT_MASK; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
DClock_Ip_Data.c2616 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_0->MUX_0_CSC),
2617 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_0->MUX_1_CSC),
2618 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_0->MUX_2_CSC),
2619 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_0->MUX_3_CSC),
2620 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_0->MUX_4_CSC),
2621 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_0->MUX_5_CSC),
2622 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_0->MUX_6_CSC),
2623 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_0->MUX_7_CSC),
2624 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_0->MUX_8_CSC),
2625 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_0->MUX_9_CSC),
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/hal_nxp-3.5.0/s32/drivers/s32k3/Mcu/src/
DClock_Ip_Divider.c171 IP_MC_CGM_0->MUX_2_DC_2 &= ~MC_CGM_MUX_2_DC_2_DIV_FMT_MASK; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_MC_CGM.h193 #define IP_MC_CGM_0 ((MC_CGM_Type *)IP_MC_CGM_0_BASE) macro
221 #define IP_MC_CGM_BASE_PTRS { IP_MC_CGM_0, IP_MC_CGM_1, IP_MC_CGM_2, IP_MC_CGM…