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Searched refs:IP_MC_CGM (Results 1 – 3 of 3) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32k3/Mcu/src/
DClock_Ip_Frequency.c1928 …if (((IP_MC_CGM->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT) != … in Clock_Ip_Get_SCS_CLK_Frequency()
1942 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_0_DC_0 & MC_CGM_MUX_0_DC_0_DE_MASK) >> MC… in Clock_Ip_Get_CORE_CLK_Frequency()
1943 …Frequency /= (((IP_MC_CGM->MUX_0_DC_0 & MC_CGM_MUX_0_DC_0_DIV_MASK) >> MC_CGM_MUX_0_DC_0_DIV_SHIFT… in Clock_Ip_Get_CORE_CLK_Frequency()
1949 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_0_DC_1 & MC_CGM_MUX_0_DC_1_DE_MASK) >> MC… in Clock_Ip_Get_AIPS_PLAT_CLK_Frequency()
1950 …Frequency /= (((IP_MC_CGM->MUX_0_DC_1 & MC_CGM_MUX_0_DC_1_DIV_MASK) >> MC_CGM_MUX_0_DC_1_DIV_SHIFT… in Clock_Ip_Get_AIPS_PLAT_CLK_Frequency()
1956 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_0_DC_2 & MC_CGM_MUX_0_DC_2_DE_MASK) >> MC… in Clock_Ip_Get_AIPS_SLOW_CLK_Frequency()
1957 …Frequency /= (((IP_MC_CGM->MUX_0_DC_2 & MC_CGM_MUX_0_DC_2_DIV_MASK) >> MC_CGM_MUX_0_DC_2_DIV_SHIFT… in Clock_Ip_Get_AIPS_SLOW_CLK_Frequency()
1963 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_0_DC_3 & MC_CGM_MUX_0_DC_3_DE_MASK) >> MC… in Clock_Ip_Get_HSE_CLK_Frequency()
1964 …Frequency /= (((IP_MC_CGM->MUX_0_DC_3 & MC_CGM_MUX_0_DC_3_DIV_MASK) >> MC_CGM_MUX_0_DC_3_DIV_SHIFT… in Clock_Ip_Get_HSE_CLK_Frequency()
1970 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_0_DC_4 & MC_CGM_MUX_0_DC_4_DE_MASK) >> MC… in Clock_Ip_Get_DCM_CLK_Frequency()
[all …]
DClock_Ip_Data.c3315 (Clock_Ip_CgmMuxType*)(&(IP_MC_CGM->MUX_0_CSC)),
3316 (Clock_Ip_CgmMuxType*)(&(IP_MC_CGM->MUX_1_CSC)),
3318 (Clock_Ip_CgmMuxType*)(&(IP_MC_CGM->MUX_2_CSC)),
3322 (Clock_Ip_CgmMuxType*)(&(IP_MC_CGM->MUX_3_CSC)),
3324 (Clock_Ip_CgmMuxType*)(&(IP_MC_CGM->MUX_4_CSC)),
3328 (Clock_Ip_CgmMuxType*)(&(IP_MC_CGM->MUX_5_CSC)),
3329 (Clock_Ip_CgmMuxType*)(&(IP_MC_CGM->MUX_6_CSC)),
3331 (Clock_Ip_CgmMuxType*)(&(IP_MC_CGM->MUX_7_CSC)),
3336 (Clock_Ip_CgmMuxType*)(&(IP_MC_CGM->MUX_8_CSC)),
3341 (Clock_Ip_CgmMuxType*)(&(IP_MC_CGM->MUX_9_CSC)),
[all …]
/hal_nxp-3.5.0/s32/drivers/s32k3/BaseNXP/header/
DS32K344_MC_CGM.h156 #define IP_MC_CGM ((MC_CGM_Type *)IP_MC_CGM_BASE) macro
160 #define IP_MC_CGM_BASE_PTRS { IP_MC_CGM }