Searched refs:IP_GPR0_PCTL (Results 1 – 2 of 2) sorted by relevance
103 #define IP_GPR0_PCTL ((GPR0_PCTL_Type *)IP_GPR0_PCTL_BASE) macro107 #define IP_GPR0_PCTL_BASE_PTRS { IP_GPR0_PCTL }
1667 …Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->FR0PCTL & GPR0_PCTL_FR0PCTL_PCTL_MASK) >> GPR0… in Clock_Ip_Get_FRAY0_CLK_Frequency()1677 …Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->FR1PCTL & GPR0_PCTL_FR1PCTL_PCTL_MASK) >> GPR0… in Clock_Ip_Get_FRAY1_CLK_Frequency()1688 …Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->GTMNANOPCTL & GPR0_PCTL_GTMNANOPCTL_PCTL_GTM_M… in Clock_Ip_Get_GTM_CLK_Frequency()1708 …Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->LIN0PCTL & GPR0_PCTL_LIN0PCTL_PCTL_MASK) >> GP… in Clock_Ip_Get_LIN0_CLK_Frequency()1718 …Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->LIN1PCTL & GPR0_PCTL_LIN1PCTL_PCTL_MASK) >> GP… in Clock_Ip_Get_LIN1_CLK_Frequency()1728 …Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->LIN2PCTL & GPR0_PCTL_LIN2PCTL_PCTL_MASK) >> GP… in Clock_Ip_Get_LIN2_CLK_Frequency()1807 … /* Apply divider value */ Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->MSCDSPIPCTL & … in Clock_Ip_Get_MSCDSPI_CLK_Frequency()1818 …Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->MSCLINPCTL & GPR0_PCTL_MSCLINPCTL_PCTL_MASK) >… in Clock_Ip_Get_MSCLIN_CLK_Frequency()1827 …Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->GTMNANOPCTL & GPR0_PCTL_GTMNANOPCTL_PCTL_NANO_… in Clock_Ip_Get_NANO_CLK_Frequency()1852 …Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->DSPI0PCTL & GPR0_PCTL_DSPI0PCTL_PCTL_MASK) >> … in Clock_Ip_Get_SPI0_CLK_Frequency()[all …]
