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Searched refs:FLEXSPI0 (Results 1 – 18 of 18) sorted by relevance

/hal_nxp-3.5.0/mcux/mcux-sdk/boards/evkmimxrt595/
Dclock_config.c72 if (FLEXSPI0 == base) in BOARD_SetFlexspiClock()
239 BOARD_SetFlexspiClock(FLEXSPI0, 0U, 2U); in BOARD_BootClockRUN()
Dboard.c365 if (base == FLEXSPI0) in BOARD_SetFlexspiClock()
428 BOARD_SetFlexspiClock(FLEXSPI0, 3U, 2U); in BOARD_FlexspiClockSafeConfig()
/hal_nxp-3.5.0/mcux/mcux-sdk/boards/evkmimxrt595/project_template/
Dclock_config.c72 if (FLEXSPI0 == base) in BOARD_SetFlexspiClock()
239 BOARD_SetFlexspiClock(FLEXSPI0, 0U, 2U); in BOARD_BootClockRUN()
Dboard.c365 if (base == FLEXSPI0) in BOARD_SetFlexspiClock()
428 BOARD_SetFlexspiClock(FLEXSPI0, 3U, 2U); in BOARD_FlexspiClockSafeConfig()
/hal_nxp-3.5.0/mcux/mcux-sdk/components/flash/mflash/mimxrt595/
Dmflash_drv.h23 #define MFLASH_FLEXSPI (FLEXSPI0)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT595S/drivers/
Dfsl_power.c621 while (!(((FLEXSPI0->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) != 0U) && in AT_QUICKACCESS_SECTION_CODE()
622 ((FLEXSPI0->STS0 & FLEXSPI_STS0_SEQIDLE_MASK) != 0U))) in AT_QUICKACCESS_SECTION_CODE()
626 FLEXSPI0->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; in AT_QUICKACCESS_SECTION_CODE()
704 initFlexSPI(FLEXSPI0); in AT_QUICKACCESS_SECTION_CODE()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT555S/drivers/
Dfsl_power.c621 while (!(((FLEXSPI0->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) != 0U) && in AT_QUICKACCESS_SECTION_CODE()
622 ((FLEXSPI0->STS0 & FLEXSPI_STS0_SEQIDLE_MASK) != 0U))) in AT_QUICKACCESS_SECTION_CODE()
626 FLEXSPI0->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; in AT_QUICKACCESS_SECTION_CODE()
704 initFlexSPI(FLEXSPI0); in AT_QUICKACCESS_SECTION_CODE()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT533S/drivers/
Dfsl_power.c621 while (!(((FLEXSPI0->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) != 0U) && in AT_QUICKACCESS_SECTION_CODE()
622 ((FLEXSPI0->STS0 & FLEXSPI_STS0_SEQIDLE_MASK) != 0U))) in AT_QUICKACCESS_SECTION_CODE()
626 FLEXSPI0->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; in AT_QUICKACCESS_SECTION_CODE()
704 initFlexSPI(FLEXSPI0); in AT_QUICKACCESS_SECTION_CODE()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT595S/project_template/
Dboard.c371 if (base == FLEXSPI0) in BOARD_SetFlexspiClock()
436 BOARD_SetFlexspiClock(FLEXSPI0, 3U, 2); in BOARD_FlexspiClockSafeConfig()
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/flexspi/
Dfsl_flexspi.c1217 #if defined(FLEXSPI0)
1221 s_flexspiIsr(FLEXSPI0, s_flexspiHandle[0]); in FLEXSPI0_DriverIRQHandler()
1267 s_flexspiIsr(FLEXSPI0, s_flexspiHandle[0]); in FLEXSPI0_FLEXSPI1_DriverIRQHandler()
/hal_nxp-3.5.0/mcux/mcux-sdk/components/power_manager/
DREADME.md124 In deep sleep, only the defined SRAM partition and the FLEXSPI0 SRAM are retained, i.e., the memory…
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5536/
DLPC5536.h13818 #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) macro
13824 #define FLEXSPI_BASE_PTRS { FLEXSPI0 }
13833 #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) macro
13837 #define FLEXSPI_BASE_PTRS { FLEXSPI0 }
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5534/
DLPC5534.h13818 #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) macro
13824 #define FLEXSPI_BASE_PTRS { FLEXSPI0 }
13833 #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) macro
13837 #define FLEXSPI_BASE_PTRS { FLEXSPI0 }
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h20692 #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) macro
20706 #define FLEXSPI_BASE_PTRS { FLEXSPI0, FLEXSPI1 }
20715 #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) macro
20723 #define FLEXSPI_BASE_PTRS { FLEXSPI0, FLEXSPI1 }
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC55S36/
DLPC55S36.h18619 #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) macro
18625 #define FLEXSPI_BASE_PTRS { FLEXSPI0 }
18634 #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) macro
18638 #define FLEXSPI_BASE_PTRS { FLEXSPI0 }
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_cm33.h20696 #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) macro
20710 #define FLEXSPI_BASE_PTRS { FLEXSPI0, FLEXSPI1 }
20719 #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) macro
20727 #define FLEXSPI_BASE_PTRS { FLEXSPI0, FLEXSPI1 }
DMIMXRT595S_dsp.h14095 #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) macro
14103 #define FLEXSPI_BASE_PTRS { FLEXSPI0, FLEXSPI1 }
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h20695 #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) macro
20709 #define FLEXSPI_BASE_PTRS { FLEXSPI0, FLEXSPI1 }
20718 #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) macro
20726 #define FLEXSPI_BASE_PTRS { FLEXSPI0, FLEXSPI1 }