| /hal_nxp-3.5.0/mcux/mcux-sdk/drivers/lpspi/ |
| D | fsl_lpspi.c | 1463 … base->FCR = (base->FCR & (~LPSPI_FCR_RXWATER_MASK)) | LPSPI_FCR_RXWATER(handle->rxWatermark);
1474 … base->FCR = (base->FCR & (~LPSPI_FCR_RXWATER_MASK)) | LPSPI_FCR_RXWATER(tmpTimes - 1U);
1704 base->FCR = (base->FCR & (~LPSPI_FCR_RXWATER_MASK)) |
1939 …base->FCR = (base->FCR & (~LPSPI_FCR_RXWATER_MASK)) | LPSPI_FCR_RXWATER(readRegRemainingTimes - 1U…
2140 base->FCR = (base->FCR & (~LPSPI_FCR_RXWATER_MASK)) |
|
| D | fsl_lpspi.h | 853 base->FCR = LPSPI_FCR_TXWATER(txWater) | LPSPI_FCR_RXWATER(rxWater); in LPSPI_SetFifoWatermarks()
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/drivers/dac_1/ |
| D | fsl_dac.c | 148 base->FCR = LPDAC_FCR_WML(config->fifoWatermarkLevel); in DAC_Init()
|
| /hal_nxp-3.5.0/s32/drivers/s32k3/BaseNXP/header/ |
| D | S32K344_LPSPI.h | 93 __IO uint32_t FCR; /**< FIFO Control, offset: 0x58 */ member
|
| D | S32K344_MU.h | 85 __IO uint32_t FCR; /**< Flag Control Register, offset: 0x100 */ member
|
| /hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/ |
| D | S32Z2_CTU.h | 96 __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x70 */ member
|
| D | S32Z2_MU.h | 85 __IO uint32_t FCR; /**< Flag Control Register, offset: 0x100 */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE14Z4/ |
| D | MKE14Z4.h | 4909 __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE15Z4/ |
| D | MKE15Z4.h | 4910 __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/K32L3A60/ |
| D | K32L3A60_cm0plus.h | 8870 __IO uint32_t FCR; /**< DAC FIFO Control Register, offset: 0x10 */ member
10499 __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */ member
|
| D | K32L3A60_cm4.h | 9505 __IO uint32_t FCR; /**< DAC FIFO Control Register, offset: 0x10 */ member
11134 __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE12Z7/ |
| D | MKE12Z7.h | 7897 __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE16Z4/ |
| D | MKE16Z4.h | 4908 __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE13Z7/ |
| D | MKE13Z7.h | 7899 __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE17Z7/ |
| D | MKE17Z7.h | 7901 __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE14Z7/ |
| D | MKE14Z7.h | 7473 __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE15Z7/ |
| D | MKE15Z7.h | 7475 __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE14F16/ |
| D | MKE14F16.h | 10081 __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE16F16/ |
| D | MKE16F16.h | 11080 __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/K32L2A31A/ |
| D | K32L2A31A.h | 8835 __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/K32L2A41A/ |
| D | K32L2A41A.h | 8835 __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE18F16/ |
| D | MKE18F16.h | 11085 __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54005/ |
| D | LPC54005.h | 10241 __O uint32_t FCR; /**< FIFO Control Register, offset: 0x8 */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54607/ |
| D | LPC54607.h | 11015 __O uint32_t FCR; /**< FIFO Control Register, offset: 0x8 */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54605/ |
| D | LPC54605.h | 10371 __O uint32_t FCR; /**< FIFO Control Register, offset: 0x8 */ member
|
