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123

/hal_nxp-3.5.0/s32/soc/s32z27/include/
DLinflexd_Uart_Ip_Defines.h84 …FALSE, (boolean) FALSE, (boolean) FALSE, (boolean) FALSE, (boolean) FALSE, (boolean) FALSE, (boole…
92 …FALSE, (boolean) FALSE, (boolean) FALSE, (boolean) FALSE, (boolean) FALSE, (boolean) FALSE, (boole…
DNetc_Eth_Ip_Cfg.h87 …UFFERS {(boolean)FALSE, (boolean)FALSE, (boolean)FALSE, (boolean)FALSE, (boolean)FALSE, (boolean)…
92 …UFFERS {(boolean)FALSE, (boolean)FALSE, (boolean)FALSE, (boolean)FALSE, (boolean)FALSE, (boolean)…
DPlatformTypes.h157 #ifndef FALSE
163 #define FALSE false macro
169 #define FALSE 0
/hal_nxp-3.5.0/s32/drivers/s32k3/Mcu/src/
DClock_Ip_Selector.c183 boolean TimeoutOccurred = FALSE; in Clock_Ip_SetCgmXCscCssClkswSwip()
205 …_Ip_apxCgm[Instance][SelectorIndex]->CSS & MC_CGM_MUX_CSS_SWIP_MASK)) && (FALSE == TimeoutOccurred… in Clock_Ip_SetCgmXCscCssClkswSwip()
207 if (FALSE == TimeoutOccurred) in Clock_Ip_SetCgmXCscCssClkswSwip()
221 …p_apxCgm[Instance][SelectorIndex]->CSS & MC_CGM_MUX_CSS_CLK_SW_MASK)) && (FALSE == TimeoutOccurred… in Clock_Ip_SetCgmXCscCssClkswSwip()
223 if (FALSE == TimeoutOccurred) in Clock_Ip_SetCgmXCscCssClkswSwip()
231 …_Ip_apxCgm[Instance][SelectorIndex]->CSS & MC_CGM_MUX_CSS_SWIP_MASK)) && (FALSE == TimeoutOccurred… in Clock_Ip_SetCgmXCscCssClkswSwip()
233 if (FALSE == TimeoutOccurred) in Clock_Ip_SetCgmXCscCssClkswSwip()
315 boolean TimeoutOccurred = FALSE; in Clock_Ip_SetCgmXCscCssClkswRampupRampdownSwip()
337 …_Ip_apxCgm[Instance][SelectorIndex]->CSS & MC_CGM_MUX_CSS_SWIP_MASK)) && (FALSE == TimeoutOccurred… in Clock_Ip_SetCgmXCscCssClkswRampupRampdownSwip()
339 if (FALSE == TimeoutOccurred) in Clock_Ip_SetCgmXCscCssClkswRampupRampdownSwip()
[all …]
DClock_Ip_Specific.c203 boolean TimeoutOccurred = FALSE; in Clock_Ip_PllPowerClockIp()
219 …while((0U == (IP_MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK56_MASK)) && (FALSE == Time… in Clock_Ip_PllPowerClockIp()
243 …while((0U == (IP_MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK57_MASK)) && (FALSE == Time… in Clock_Ip_PllPowerClockIp()
261 boolean TimeoutOccurred = FALSE; in Clock_Ip_PowerClockIpModules()
279 …while((0U == (IP_MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK53_MASK)) && (FALSE == Time… in Clock_Ip_PowerClockIpModules()
303 …while((0U == (IP_MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK51_MASK)) && (FALSE == Time… in Clock_Ip_PowerClockIpModules()
327 …while((0U == (IP_MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK47_MASK)) && (FALSE == Time… in Clock_Ip_PowerClockIpModules()
350 …while((0U == (IP_MC_ME->PRTN1_COFB0_STAT & MC_ME_PRTN1_COFB0_STAT_BLOCK24_MASK)) && (FALSE == Time… in Clock_Ip_PowerClockIpModules()
529 if (FALSE == Clock_Ip_bObjectsAreInitialized) in Clock_Ip_ClockInitializeObjects()
DClock_Ip_ExtOsc.c214 boolean TimeoutOccurred = FALSE; in Clock_Ip_CompleteFxoscOsconBypEocvGmSel()
242 while ((0U == FxoscStatus) && (FALSE == TimeoutOccurred)); in Clock_Ip_CompleteFxoscOsconBypEocvGmSel()
344 boolean TimeoutOccurred = FALSE; in Clock_Ip_CompleteSxoscOsconEocv()
366 while ((0U == SxoscStatus) && (FALSE == TimeoutOccurred)); in Clock_Ip_CompleteSxoscOsconEocv()
DClock_Ip_IntOsc.c211 boolean TimeoutOccurred = FALSE; in Clock_Ip_SetFircDivSelHSEb()
250 while ((CLOCK_IP_WFI_EXECUTED != WfiStatus) && (FALSE == TimeoutOccurred)); in Clock_Ip_SetFircDivSelHSEb()
252 if (FALSE == TimeoutOccurred) in Clock_Ip_SetFircDivSelHSEb()
DClock_Ip_Gate.c138 boolean TimeoutOccurred = FALSE; in Clock_Ip_ClockSetGateMcMePartitionCollectionClockRequest()
176 …etPartitions[Partition]->PRTN_COFB_STAT[Collection] & EnableRequest)) && (FALSE == TimeoutOccurred… in Clock_Ip_ClockSetGateMcMePartitionCollectionClockRequest()
206 …itions[Partition]->PRTN_COFB_STAT[Collection] & EnableRequest) != 0U) && (FALSE == TimeoutOccurred… in Clock_Ip_ClockSetGateMcMePartitionCollectionClockRequest()
/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Selector.c173 boolean TimeoutOccurred = FALSE; in Clock_Ip_SetCgmXCscCssClkswSwip()
186 …_Ip_apxCgm[Instance][SelectorIndex]->CSS & MC_CGM_MUX_CSS_SWIP_MASK)) && (FALSE == TimeoutOccurred… in Clock_Ip_SetCgmXCscCssClkswSwip()
188 if (FALSE == TimeoutOccurred) in Clock_Ip_SetCgmXCscCssClkswSwip()
202 …p_apxCgm[Instance][SelectorIndex]->CSS & MC_CGM_MUX_CSS_CLK_SW_MASK)) && (FALSE == TimeoutOccurred… in Clock_Ip_SetCgmXCscCssClkswSwip()
204 if (FALSE == TimeoutOccurred) in Clock_Ip_SetCgmXCscCssClkswSwip()
212 …_Ip_apxCgm[Instance][SelectorIndex]->CSS & MC_CGM_MUX_CSS_SWIP_MASK)) && (FALSE == TimeoutOccurred… in Clock_Ip_SetCgmXCscCssClkswSwip()
214 if (FALSE == TimeoutOccurred) in Clock_Ip_SetCgmXCscCssClkswSwip()
254 boolean TimeoutOccurred = FALSE; in Clock_Ip_ResetCgmXCscCssCsGrip()
266 …ck_Ip_apxCgm[Instance][SelectorIndex]->CSS & MC_CGM_MUX_CSS_CS_MASK)) && (FALSE == TimeoutOccurred… in Clock_Ip_ResetCgmXCscCssCsGrip()
268 if (FALSE == TimeoutOccurred) in Clock_Ip_ResetCgmXCscCssCsGrip()
[all …]
DClock_Ip_Divider.c144 boolean TimeoutOccurred = FALSE; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
181 … while ((MC_CGM_MUX_DIV_UPD_STAT_DIV_STAT_PENDING == DividerStatus) && (FALSE == TimeoutOccurred)); in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
183 if (FALSE == TimeoutOccurred) in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
215 boolean TimeoutOccurred = FALSE; in Clock_Ip_SetCgmXDeDivStatWithoutPhaseWithTrigger()
240 … while ((MC_CGM_MUX_DIV_UPD_STAT_DIV_STAT_PENDING == DividerStatus) && (FALSE == TimeoutOccurred)); in Clock_Ip_SetCgmXDeDivStatWithoutPhaseWithTrigger()
243 if (FALSE == TimeoutOccurred) in Clock_Ip_SetCgmXDeDivStatWithoutPhaseWithTrigger()
DClock_Ip_Pll.c228 boolean TimeoutOccurred = FALSE; in Clock_Ip_CompletePlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
244 while ((0U == PllLockStatus) && (FALSE == TimeoutOccurred)); in Clock_Ip_CompletePlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
330 boolean TimeoutOccurred = FALSE; in Clock_Ip_CompletePlldigRdivMfiMfnSdmen()
346 while ((0U == PllLockStatus) && (FALSE == TimeoutOccurred)); in Clock_Ip_CompletePlldigRdivMfiMfnSdmen()
424 boolean TimeoutOccurred = FALSE; in Clock_Ip_CompleteLfastPLL()
439 while ((0U != PllEnableStatus) && (FALSE == TimeoutOccurred)); in Clock_Ip_CompleteLfastPLL()
453 while ((1U != PllLockStatus) && (FALSE == TimeoutOccurred)); in Clock_Ip_CompleteLfastPLL()
DClock_Ip_FracDiv.c169 boolean TimeoutOccurred = FALSE; in Clock_Ip_CompleteDfsMfiMfn()
190 while ((0U == DfsPortStatus) && (FALSE == TimeoutOccurred)); in Clock_Ip_CompleteDfsMfiMfn()
192 if (FALSE != TimeoutOccurred) in Clock_Ip_CompleteDfsMfiMfn()
/hal_nxp-3.5.0/s32/drivers/s32k3/Pwm/include/
DEmios_Pwm_Ip_HwAccess.h141 return (((Base->MCR & eMIOS_MCR_FRZ_MASK) >> eMIOS_MCR_FRZ_SHIFT) == 0U)? FALSE : TRUE; in Emios_Pwm_Ip_GetDebugMode()
166 …DIS & (uint32)((uint32)eMIOS_OUDIS_OU0_MASK << (uint32)Channel)) >> Channel) == 0U) ? TRUE : FALSE; in Emios_Pwm_Ip_GetOutputUpdate()
201 … & (uint32)((uint32)eMIOS_UCDIS_UCDIS0_MASK << (uint32)Channel)) >> Channel) == 0U) ? TRUE : FALSE; in Emios_Pwm_Ip_GetChannelEnable()
282 uint8 ValueConvert = (Value == FALSE)? 0U : 1U; in Emios_Pwm_Ip_SetFreezeEnable()
296 uint8 ValueConvert = (Value == FALSE)? 0U : 1U; in Emios_Pwm_Ip_SetOutDisable()
325 uint8 ValueConvert = (Value == FALSE)? 0U : 1U; in Emios_Pwm_Ip_SetPrescalerEnable()
343 uint8 ValueConvert = (Value == FALSE)? 0U : 1U; in Emios_Pwm_Ip_SetDMARequest()
358 return (((Base->CH.UC[Channel].C & eMIOS_C_DMA_MASK) >> eMIOS_C_DMA_SHIFT) == 0U)? FALSE : TRUE; in Emios_Pwm_Ip_GetDMARequest()
373 uint8 ValueConvert = (Value == FALSE)? 0U : 1U; in Emios_Pwm_Ip_SetInterruptRequest()
388 return (((Base->CH.UC[Channel].C & eMIOS_C_FEN_MASK) >> eMIOS_C_FEN_SHIFT) == 0U)? FALSE : TRUE; in Emios_Pwm_Ip_GetInterruptRequest()
[all …]
/hal_nxp-3.5.0/s32/drivers/s32ze/Uart/src/
DLinflexd_Uart_Ip.c263 boolean ResetIdle = FALSE; in Linflexd_Uart_Ip_SetBaudrate()
264 boolean IsReturn = FALSE; in Linflexd_Uart_Ip_SetBaudrate()
399 UartStatePtr->IsDriverInitialized = FALSE; in Linflexd_Uart_Ip_Init()
416 Linflexd_Uart_Ip_SetTransmitterState(Base, FALSE); in Linflexd_Uart_Ip_Init()
417 Linflexd_Uart_Ip_SetReceiverState(Base, FALSE); in Linflexd_Uart_Ip_Init()
461 Linflexd_Uart_Ip_SetInterruptMode(Base, LINFLEXD_DATA_TRANSMITTED_INT, FALSE); in Linflexd_Uart_Ip_Deinit()
463 Linflexd_Uart_Ip_SetInterruptMode(Base, LINFLEXD_DATA_RECEPTION_COMPLETE_INT, FALSE); in Linflexd_Uart_Ip_Deinit()
467 Linflexd_Uart_Ip_SetInterruptMode(Base, LINFLEXD_FRAME_ERROR_INT, FALSE); in Linflexd_Uart_Ip_Deinit()
468 Linflexd_Uart_Ip_SetInterruptMode(Base, LINFLEXD_BUFFER_OVERRUN_INT, FALSE); in Linflexd_Uart_Ip_Deinit()
473 Linflexd_Uart_Ip_SetInterruptMode(Base, LINFLEXD_TIMEOUT_INT, FALSE); in Linflexd_Uart_Ip_Deinit()
[all …]
/hal_nxp-3.5.0/s32/drivers/s32k3/BaseNXP/src/
DOsIf_Timer_System.c289 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_Init()
331 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_GetCounter()
343 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_GetCounter()
385 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_GetElapsed()
397 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_GetElapsed()
440 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_SetTimerFrequency()
452 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_SetTimerFrequency()
489 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_MicrosToTicks()
501 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_MicrosToTicks()
/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/src/
DOsIf_Timer_System.c289 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_Init()
326 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_GetCounter()
338 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_GetCounter()
380 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_GetElapsed()
392 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_GetElapsed()
435 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_SetTimerFrequency()
447 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_SetTimerFrequency()
484 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_MicrosToTicks()
496 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_MicrosToTicks()
/hal_nxp-3.5.0/s32/drivers/s32ze/Spi/src/
DSpi_Ip.c288 boolean ErrorFlag = (boolean)FALSE; in Spi_Ip_TransferProcess()
312 if((boolean)FALSE == State->PhyUnitConfig->SlaveMode) in Spi_Ip_TransferProcess()
346 if(((boolean)TRUE == ErrorFlag) || ((boolean)FALSE == State->KeepCs)) in Spi_Ip_TransferProcess()
637 boolean ClearCS = (boolean)FALSE; in Spi_Ip_DmaConfig()
638 boolean EnScatterGather = (boolean)FALSE; in Spi_Ip_DmaConfig()
650 if((boolean)FALSE == State->KeepCs) in Spi_Ip_DmaConfig()
675 if((boolean)FALSE == State->PhyUnitConfig->SlaveMode) in Spi_Ip_DmaConfig()
689 EnScatterGather = (boolean)FALSE; in Spi_Ip_DmaConfig()
699 EnScatterGather = (boolean)FALSE; in Spi_Ip_DmaConfig()
832 if((boolean)FALSE == State->PhyUnitConfig->SlaveMode) in Spi_Ip_DmaConfig()
[all …]
/hal_nxp-3.5.0/s32/drivers/s32k3/Pwm/src/
DEmios_Pwm_Ip.c239 boolean Ret = FALSE; in Emios_Pwm_Ip_ValidateMode()
242 … (((Emios_Pwm_Ip_aChannelModes[Instance][(uint8)Mode] >> Channel) & 0x01UL) == 1UL) ? TRUE : FALSE; in Emios_Pwm_Ip_ValidateMode()
487 Emios_Pwm_Ip_SetInterruptRequest(Base, Channel, FALSE); in Emios_Pwm_Ip_SetDutyCycleOpwfmb()
498 Emios_Pwm_Ip_SetInterruptRequest(Base, Channel, FALSE); in Emios_Pwm_Ip_SetDutyCycleOpwfmb()
505 Emios_Pwm_Ip_SetInterruptRequest(Base, Channel, FALSE); in Emios_Pwm_Ip_SetDutyCycleOpwfmb()
512 …ios_Pwm_Ip_aCheckEnableNotif[eMios_Pwm_Ip_IndexInChState[Instance][Channel]] == 0U)? FALSE : TRUE); in Emios_Pwm_Ip_SetDutyCycleOpwfmb()
553 Emios_Pwm_Ip_SetInterruptRequest(Base, Channel, FALSE); in Emios_Pwm_Ip_SetDutyCycleOpwfm()
570 Emios_Pwm_Ip_SetInterruptRequest(Base, Channel, FALSE); in Emios_Pwm_Ip_SetDutyCycleOpwfm()
583 Emios_Pwm_Ip_SetInterruptRequest(Base, Channel, FALSE); in Emios_Pwm_Ip_SetDutyCycleOpwfm()
596 …ios_Pwm_Ip_aCheckEnableNotif[eMios_Pwm_Ip_IndexInChState[Instance][Channel]] == 0U)? FALSE : TRUE); in Emios_Pwm_Ip_SetDutyCycleOpwfm()
[all …]
/hal_nxp-3.5.0/s32/drivers/s32k3/Fls/include/
DQspi_Ip_HwAccess.h94 return (0U == RegValue)? TRUE : FALSE; in Qspi_Ip_GetClrTxStatus()
116 return (0U == RegValue)? TRUE : FALSE; in Qspi_Ip_GetClrAhbStatus()
448 return (RegValue != 0U)? TRUE : FALSE; in Qspi_Ip_DLLGetSlaveLockStatusA()
451 return FALSE; in Qspi_Ip_DLLGetSlaveLockStatusA()
465 return (RegValue != 0U)? TRUE : FALSE; in Qspi_Ip_DLLGetLockStatusA()
468 return FALSE; in Qspi_Ip_DLLGetLockStatusA()
481 return (RegValue != 0U)? TRUE : FALSE; in Qspi_Ip_DLLGetErrorStatusA()
484 return FALSE; in Qspi_Ip_DLLGetErrorStatusA()
715 return (RegValue != 0U)? TRUE : FALSE; in Qspi_Ip_GetBusyStatus()
739 return (RegValue != 0U)? TRUE : FALSE; in Qspi_Ip_GetRxDataEvent()
[all …]
/hal_nxp-3.5.0/s32/drivers/s32k3/BaseNXP/include/
DPlatformTypes.h152 #ifndef FALSE
158 #define FALSE false macro
164 #define FALSE 0
/hal_nxp-3.5.0/s32/drivers/s32k3/Icu/src/
DWkpu_Ip.c495 FALSE); in Wkpu_Ip_DisableInterrupt()
502 FALSE); in Wkpu_Ip_DisableInterrupt()
733 FALSE); in Wkpu_Ip_SetActivationCondition()
741 FALSE); in Wkpu_Ip_SetActivationCondition()
755 FALSE); in Wkpu_Ip_SetActivationCondition()
761 FALSE); in Wkpu_Ip_SetActivationCondition()
802 boolean bstate = FALSE; in Wkpu_Ip_GetInputState()
867 Wkpu_Ip_u32ChState[Wkpu_Ip_IndexInChState[hwChannel]].notificationEnable = FALSE; in Wkpu_Ip_DisableNotification()
989 if (Wkpu_Ip_IsNMIConfigLock(base, coreShift) == FALSE) in Wkpu_Ip_DeinitNMI()
/hal_nxp-3.5.0/s32/drivers/s32ze/Can_CANEXCEL/src/
DCanEXCEL_Ip.c122 …0U == (base->SYSMC & (CANXL_SIC_SYSMC_LPMREQ_MASK | CANXL_SIC_SYSMC_FRZREQ_MASK))) ? TRUE : FALSE); in Canexcel_Ip_GetStartMode()
259 Canexcel_Ip_apxState[instance]->rxFifo.isXLFrame = FALSE; in Canexcel_Ip_Init()
292 Canexcel_Ip_apxState[instance]->isIntActive = FALSE; in Canexcel_Ip_Init()
347 DevAssert(FALSE); in Canexcel_Ip_ConfigRx()
358 state->msgDesc[descNo].isXLFrame = FALSE; in Canexcel_Ip_ConfigRx()
373 state->msgDesc[descNo].isXLFrame = FALSE; in Canexcel_Ip_ConfigRx()
426 if (isPolling == FALSE) in Canexcel_Ip_ReceiveFD()
437 if (isPolling == FALSE) in Canexcel_Ip_ReceiveXL()
499 Canexcel_Ip_apxState[instance]->msgDesc[mbIdx].isXLFrame = FALSE; in Canexcel_Ip_ConfigFdTx()
536 if (info->is_polling == FALSE) in Canexcel_Ip_SendFDMsg()
[all …]
/hal_nxp-3.5.0/s32/drivers/s32ze/Eth_NETC/src/
DNetc_Eth_Ip.c127 boolean LatestTxTimestampValidFlag = (boolean)FALSE;
319 return ((*ElapsedTimeInOut >= TimeoutTicks) ? TRUE : FALSE); in Netc_Eth_Ip_TimeoutExpired()
361 config->stateStructure->LockTxBuffDescr[u8TxBDIdx][currBDIdx] = FALSE; in Netc_Eth_Ip_InitStateStructure()
410 Netc_Eth_Ip_TxTimestampInfoBuff[ctrlIndex][currBDIdx].TxTimestampFlag = FALSE; in Netc_Eth_Ip_InitTxBD()
730 if(FALSE == MACFilterHashTableAddrs[CtrlIndex][CurrentEntry].EntryStatus) in Netc_Eth_Ip_AddMACFilterEntry()
750 boolean MatchedEntry = FALSE; in Netc_Eth_Ip_DeleteMACFilterEntry()
767 if(MatchedEntry == FALSE) in Netc_Eth_Ip_DeleteMACFilterEntry()
780 MACFilterHashTableAddrs[CtrlIndex][CurrentEntry].EntryStatus = FALSE; in Netc_Eth_Ip_DeleteMACFilterEntry()
1146 … (Netc_Eth_Ip_apxState[ctrlIndex]->TxPacketsThreshold[0U] != 0U)) ? TRUE : FALSE ; in Netc_Eth_Ip_EnableController()
1148 … (Netc_Eth_Ip_apxState[ctrlIndex]->RxPacketsThreshold[0U] != 0U)) ? TRUE : FALSE ; in Netc_Eth_Ip_EnableController()
[all …]
/hal_nxp-3.5.0/s32/drivers/s32k3/Mcl/src/
DEmios_Mcl_Ip.c91 {(boolean)FALSE, (uint8)255}
328 if (Emios_Ip_axIpIsInitialized[Instance].instanceInitState == FALSE) in Emios_Mcl_Ip_Deinit()
354 Emios_Ip_axChState[Instance][CurrentChannel].channelInitState = FALSE; in Emios_Mcl_Ip_Deinit()
357 Emios_Ip_axIpIsInitialized[Instance].instanceInitState = FALSE; in Emios_Mcl_Ip_Deinit()
391 boolean Valid = FALSE; in Emios_Mcl_Ip_ValidateChannel()
460 boolean Valid = FALSE; in Emios_Mcl_Ip_ValidateMultiCoreInit()
/hal_nxp-3.5.0/s32/drivers/s32ze/EthSwt_NETC/src/
DNetc_EthSwt_Ip.c140 …AwareShaperEnabled[NETC_ETHSWT_NUMBER_OF_PORTS] = {(boolean)FALSE, (boolean)FALSE, (boolean)FALSE};
143 static boolean MirrorConfigurationDone = FALSE;
352 return ((*ElapsedTimeInOut >= TimeoutTicks) ? TRUE : FALSE); in Netc_EthSwt_Ip_TimeoutExpired()
489 *PortEnable = FALSE; in Netc_EthSwt_Ip_GetPortMode()
500 *PortEnable = FALSE; in Netc_EthSwt_Ip_GetPortMode()
512 *PortEnable = FALSE; in Netc_EthSwt_Ip_GetPortMode()
951 …MECAPE_MASK) >> NETC_ETHSWT_IP_FDBTABLE_CFGE_CONFIG_FIELD_TIMECAPE_SHIFT) != 0x0UL) ? TRUE : FALSE; in Netc_EthSwt_Ip_QueryFdbTableEntry()
952 …DYNAMIC_MASK) >> NETC_ETHSWT_IP_FDBTABLE_CFGE_CONFIG_FIELD_DYNAMIC_SHIFT) != 0x0UL) ? TRUE : FALSE; in Netc_EthSwt_Ip_QueryFdbTableEntry()
954 …ELD_IMIRE_MASK) >> NETC_ETHSWT_IP_FDBTABLE_CFGE_CONFIG_FIELD_IMIRE_SHIFT) != 0x0UL) ? TRUE : FALSE; in Netc_EthSwt_Ip_QueryFdbTableEntry()
1050 …DevAssert(FdbTableEntry->DynamicEntry == FALSE); /* users should not be allowed to add dynamic … in Netc_EthSwt_Ip_AddOrUpdateFdbTableEntry()
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