1.. zephyr:board:: imx95_evk
2
3Overview
4********
5
6The i.MX95 EVK (IMX95LPD5EVK-19) board is a platform designed to show the
7most commonly used features of the i.MX 95 automotive applications processor.
8It is an entry-level development board, which helps developers to get familiar
9with the processor before investing a large amount of resources in more
10specific designs. The i.MX95 device on the board comes in a compact
1119 x 19 mm package.
12
13Hardware
14********
15
16- i.MX 95 automotive applications processor
17
18  - The processor integrates up to six Arm Cortex-A55 cores, and supports
19    functional safety with built-in Arm Cortex-M33 and -M7 cores
20
21- DRAM memory: 128-Gbit LPDDR5 DRAM
22- eMMC: 64 GB Micron eMMC
23- SPI NOR flash memory: 1 Gbit octal flash memory
24- USB interface: Two USB ports: Type-A and Type-C
25- Audio codec interface
26
27  - One audio codec WM8962BECSN/R with one TX and RX lane
28  - One 3.5 mm 4-pole CTIA standard audio jack
29  - One 4-pin connector to connect speaker
30
31- Ethernet interface
32
33  - ENET2 controller
34
35    - Connects to a 60-pin Ethernet connector
36    - Supports Ethernet PHY daughter cards that can be configured to operate
37      at 100 Mbit/s or 1000 Mbit/s
38
39  - ENET1 controller
40
41    - Supports 100 Mbit/s or 1000 Mbit/s RGMII Ethernet with one RJ45
42      connector connected with an external PHY, RTL8211
43
44  - 10 Gbit Ethernet controller
45
46    - Supports XFI and USXGMII interfaces with one 10 Gbit RJ45 ICM connected
47      with an external PHY, Marvell AQR113C
48
49- M.2 interface: One Wi-Fi/Bluetooth Murata Type-2EL module based on NXP AW693
50  chip supporting 2x2 Wi-Fi 6 and Bluetooth 5.2
51
52- MIPI CSI interface: Connects to one 36-pin miniSAS connector using x4 lane
53  configuration
54- MIPI CSIDSI interface: Connects to one 36-pin miniSAS connector using x4 lane
55  configuration
56- LVDS interface: two mini-SAS connectors each with x4-lane configuration
57- CAN interface: Two 4-pin CAN headers for external connection
58- SD card interface: one 4-bit SD3.0 microSD card
59- I2C interface: I2C1 to I2C7 controllers
60- FT4232H I2C interface: PCT2075 temperature sensor and current monitoring devices
61- DMIC interface: two digital microphones (DMIC) providing a single-bit PDM output
62- ADC interface: two 4-channel ADC header
63- Audio board interface
64
65  - Supports PCIe x4 slot for Quantum board connection
66  - Supports PCIe x8 slot for Audio I/O board connection
67
68- Debug interface
69
70  - One USB-to-UART/MPSSE device, FT4232H
71  - One USB 2.0 Type-C connector (J31) for FT4232H provides quad serial ports
72
73Supported Features
74==================
75
76The Zephyr ``imx95_evk/mimx9596/m7`` board target supports the following hardware features:
77
78+-----------+------------+-------------------------------------+
79| Interface | Controller | Driver/Component                    |
80+===========+============+=====================================+
81| NVIC      | on-chip    | interrupt controller                |
82+-----------+------------+-------------------------------------+
83| SYSTICK   | on-chip    | systick                             |
84+-----------+------------+-------------------------------------+
85| CLOCK     | on-chip    | clock_control                       |
86+-----------+------------+-------------------------------------+
87| PINMUX    | on-chip    | pinmux                              |
88+-----------+------------+-------------------------------------+
89| UART      | on-chip    | serial port                         |
90+-----------+------------+-------------------------------------+
91| I2C       | on-chip    | i2c                                 |
92+-----------+------------+-------------------------------------+
93| TPM       | on-chip    | tpm                                 |
94+-----------+------------+-------------------------------------+
95| SPI       | on-chip    | spi                                 |
96+-----------+------------+-------------------------------------+
97| GPIO      | on-chip    | gpio                                |
98+-----------+------------+-------------------------------------+
99
100The Zephyr ``imx95_evk/mimx9596/a55`` and ``imx95_evk/mimx9596/a55/smp`` board targets support
101the following hardware features:
102
103+-----------+------------+-------------------------------------+
104| Interface | Controller | Driver/Component                    |
105+===========+============+=====================================+
106| GIC-v4    | on-chip    | interrupt controller                |
107+-----------+------------+-------------------------------------+
108| ARM TIMER | on-chip    | system clock                        |
109+-----------+------------+-------------------------------------+
110| CLOCK     | on-chip    | clock_control                       |
111+-----------+------------+-------------------------------------+
112| PINMUX    | on-chip    | pinmux                              |
113+-----------+------------+-------------------------------------+
114| UART      | on-chip    | serial port                         |
115+-----------+------------+-------------------------------------+
116| I2C       | on-chip    | i2c                                 |
117+-----------+------------+-------------------------------------+
118| TPM       | on-chip    | TPM Counter                         |
119+-----------+------------+-------------------------------------+
120
121System Clock
122------------
123
124This board configuration uses a system clock frequency of 24 MHz for Cortex-A55.
125Cortex-A55 Core runs up to 1.8 GHz.
126Cortex-M7 Core runs up to 800MHz in which SYSTICK runs on same frequency.
127
128Serial Port
129-----------
130
131This board configuration uses a single serial communication channel with the
132CPU's UART1 for Cortex-A55, UART3 for Cortex-M7.
133
134TPM
135---
136
137Two channels are enabled on TPM2 for PWM for M7. Signals can be observerd with
138oscilloscope.
139Channel 2 signal routed to resistance R881.
140Channel 3 signal routed to resistance R882.
141
142SPI
143---
144
145The EVK board need to be reworked to solder R1217/R1218/R1219/R1220 with 0R resistances.
146SPI1 on J35 is enabled for M7.
147
148
149Programming and Debugging (A55)
150*******************************
151
152Use this configuration to run basic Zephyr applications and kernel tests,
153for example, with the :zephyr:code-sample:`synchronization` sample:
154
1551. Build and run the Non-SMP application
156
157.. zephyr-app-commands::
158   :zephyr-app: samples/synchronization
159   :host-os: unix
160   :board: imx95_evk/mimx9596/a55
161   :goals: build
162
163This will build an image (zephyr.bin) with the synchronization sample app.
164
165Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and
166plug the SD card into the board. Power it up and stop the u-boot execution at
167prompt.
168
169Use U-Boot to load and kick zephyr.bin to Cortex-A55 Core1:
170
171.. code-block:: console
172
173    fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; cpu 1 release 0xd0000000
174
175
176Or use the following command to kick zephyr.bin to Cortex-A55 Core0:
177
178.. code-block:: console
179
180    fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; go 0xd0000000
181
182
183It will display the following console output:
184
185.. code-block:: console
186
187    *** Booting Zephyr OS build v3.6.0-4569-g483c01ca11a7 ***
188    thread_a: Hello World from cpu 0 on imx95_evk!
189    thread_b: Hello World from cpu 0 on imx95_evk!
190    thread_a: Hello World from cpu 0 on imx95_evk!
191    thread_b: Hello World from cpu 0 on imx95_evk!
192    thread_a: Hello World from cpu 0 on imx95_evk!
193
1942. Build and run the SMP application
195
196.. zephyr-app-commands::
197   :zephyr-app: samples/synchronization
198   :host-os: unix
199   :board: imx95_evk/mimx9596/a55/smp
200   :goals: build
201
202This will build an image (zephyr.bin) with the synchronization sample app.
203
204Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and
205plug the SD card into the board. Power it up and stop the u-boot execution at
206prompt.
207
208Use the following command to kick zephyr.bin to Cortex-A55 Core0:
209
210.. code-block:: console
211
212    fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; go 0xd0000000
213
214
215It will display the following console output:
216.. code-block:: console
217
218    *** Booting Zephyr OS build v3.7.0-rc3-15-g2f0beaea144a ***
219    Secondary CPU core 1 (MPID:0x100) is up
220    Secondary CPU core 2 (MPID:0x200) is up
221    Secondary CPU core 3 (MPID:0x300) is up
222    Secondary CPU core 4 (MPID:0x400) is up
223    Secondary CPU core 5 (MPID:0x500) is up
224    thread_a: Hello World from cpu 0 on imx95_evk!
225    thread_b: Hello World from cpu 4 on imx95_evk!
226    thread_a: Hello World from cpu 0 on imx95_evk!
227    thread_b: Hello World from cpu 3 on imx95_evk!
228    thread_a: Hello World from cpu 0 on imx95_evk!
229    thread_b: Hello World from cpu 1 on imx95_evk!
230    thread_a: Hello World from cpu 0 on imx95_evk!
231    thread_b: Hello World from cpu 5 on imx95_evk!
232    thread_a: Hello World from cpu 0 on imx95_evk!
233    thread_b: Hello World from cpu 2 on imx95_evk!
234
235Programming and Debugging (M7)
236******************************
237
238The i.MX System Manager (SM) is used on i.MX95, which is an application that runs on
239Cortex-M33 processor. The Cortex-M33 is the boot core, runs the boot ROM which loads
240the SM (and other boot code), and then branches to the SM. The SM then configures some
241aspects of the hardware such as isolation mechanisms and then starts other cores in the
242system. After starting these cores, it enters a service mode where it provides access
243to clocking, power, sensor, and pin control via a client RPC API based on ARM's
244`System Control and Management Interface (SCMI)`_.
245
246To program M7, an i.MX container image ``flash.bin`` must be made, which contains
247multiple elements required, like ELE+V2X firmware, System Manager, TCM OEI, Cortex-M7
248image and so on.
249
250The steps making flash.bin and programming should refer to ``Getting Started with
251MCUXpresso SDK for IMX95LPD5EVK-19.pdf`` in i.MX95 `MCUX SDK release`_. Note that
252for the DDR variant, one should use the Makefile targets containing the ``ddr`` keyword.
253
254See ``4.2 Run an example application``, just rename ``zephyr.bin`` to ``m7_image.bin``
255to make flash.bin and program to SD/eMMC.
256
257Zephyr supports two M7-based i.MX95 boards: ``imx95_evk/mimx9596/m7`` and
258``imx95_evk/mimx9596/m7/ddr``. The main difference between them is the memory
259used. ``imx95_evk/mimx9596/m7`` uses TCM (ITCM for code and, generally, read-only
260data and DTCM for R/W data), while ``imx95_evk/mimx9596/m7/ddr`` uses DDR.
261
2621. Building the :zephyr:code-sample:`hello_world` application for the TCM-based board
263
264.. zephyr-app-commands::
265   :zephyr-app: samples/hello_world
266   :board: imx95_evk/mimx9596/m7
267   :goals: build
268
2692. Building the :zephyr:code-sample:`hello_world` application for the DDR-based board
270
271.. zephyr-app-commands::
272   :zephyr-app: samples/hello_world
273   :board: imx95_evk/mimx9596/m7/ddr
274   :goals: build
275
276After making flash.bin and program to SD/eMMC, open a serial terminal, and reset the
277board. For the ``imx95_evk/mimx9596/m7`` board you should see something like:
278
279.. code-block:: console
280
281   *** Booting Zephyr OS build v3.6.0-4569-g483c01ca11a7 ***
282   Hello World! imx95_evk/mimx9596/m7
283
284while, for the ``imx95_evk/mimx9596/m7/ddr`` board, you should get the following output:
285
286.. code-block:: console
287
288   *** Booting Zephyr OS build v3.6.0-4569-g483c01ca11a7 ***
289   Hello World! imx95_evk/mimx9596/m7/ddr
290
291.. _System Control and Management Interface (SCMI):
292   https://developer.arm.com/documentation/den0056/latest/
293
294.. _i.MX Linux BSP release:
295   https://www.nxp.com/design/design-center/software/embedded-software/i-mx-software/embedded-linux-for-i-mx-applications-processors:IMXLINUX
296
297.. _MCUX SDK release:
298   https://mcuxpresso.nxp.com/
299
300.. include:: ../../common/board-footer.rst
301   :start-after: nxp-board-footer
302
303.. _NXP website:
304   https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-9-processors/i-mx-95-applications-processor-family-high-performance-safety-enabled-platform-with-eiq-neutron-npu:iMX95
305