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Searched refs:ENET0PCTL (Results 1 – 2 of 2) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_GPR1_PCTL.h85 __IO uint32_t ENET0PCTL; /**< ENET_0 Clock Control Enable, offset: 0x30 */ member
/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Frequency.c2622 …Frequency &= Clock_Ip_u32EnableGate[((IP_GPR1_PCTL->ENET0PCTL & GPR1_PCTL_ENET0PCTL_PCTL_MASK) >> … in Clock_Ip_Get_ENET0_CLK_Frequency()