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Searched refs:EDMACEPCTL (Results 1 – 2 of 2) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_GPR3_PCTL.h74 __IO uint32_t EDMACEPCTL; /**< CE_eDMA Clock Control Enable, offset: 0x4 */ member
/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Frequency.c2557 …Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->EDMACEPCTL & GPR3_PCTL_EDMACEPCTL_PCTL_MASK) >… in Clock_Ip_Get_CE_EDMA_CLK_Frequency()