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Searched refs:EDMA5PCTL (Results 1 – 2 of 2) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_GPR5_PCTL.h73 __IO uint32_t EDMA5PCTL; /**< eDMA_5 Clock Control Enable, offset: 0x0 */ member
/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Frequency.c2419 …Frequency &= Clock_Ip_u32EnableGate[((IP_GPR5_PCTL->EDMA5PCTL & GPR5_PCTL_EDMA5PCTL_PCTL_1_MASK) >… in Clock_Ip_Get_DMACRC5_CLK_Frequency()
2462 …Frequency &= Clock_Ip_u32EnableGate[((IP_GPR5_PCTL->EDMA5PCTL & GPR5_PCTL_EDMA5PCTL_PCTL_2_MASK) >… in Clock_Ip_Get_DMAMUX5_CLK_Frequency()
2603 …Frequency &= Clock_Ip_u32EnableGate[((IP_GPR5_PCTL->EDMA5PCTL & GPR5_PCTL_EDMA5PCTL_PCTL_0_MASK) >… in Clock_Ip_Get_EDMA5_CLK_Frequency()
3728 …Frequency &= Clock_Ip_u32EnableGate[((IP_GPR5_PCTL->EDMA5PCTL & GPR5_PCTL_EDMA5PCTL_PCTL_3_MASK) >… in Clock_Ip_Get_PIT5_CLK_Frequency()