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Searched refs:EDMA4PCTL (Results 1 – 2 of 2) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_GPR4_PCTL.h75 __IO uint32_t EDMA4PCTL; /**< eDMA_4 Clock Control Enable, offset: 0x8 */ member
/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Frequency.c2409 …Frequency &= Clock_Ip_u32EnableGate[((IP_GPR4_PCTL->EDMA4PCTL & GPR4_PCTL_EDMA4PCTL_PCTL_1_MASK) >… in Clock_Ip_Get_DMACRC4_CLK_Frequency()
2451 …divider value */ Frequency &= Clock_Ip_u32EnableGate[((IP_GPR4_PCTL->EDMA4PCTL & GPR4_PCTL_EDMA… in Clock_Ip_Get_DMAMUX4_CLK_Frequency()
2593 …Frequency &= Clock_Ip_u32EnableGate[((IP_GPR4_PCTL->EDMA4PCTL & GPR4_PCTL_EDMA4PCTL_PCTL_0_MASK) >… in Clock_Ip_Get_EDMA4_CLK_Frequency()
3717 …Frequency &= Clock_Ip_u32EnableGate[((IP_GPR4_PCTL->EDMA4PCTL & GPR4_PCTL_EDMA4PCTL_PCTL_3_MASK) >… in Clock_Ip_Get_PIT4_CLK_Frequency()