Searched refs:DividerIndex (Results 1 – 5 of 5) sorted by relevance
140 uint32 DividerIndex; in Clock_Ip_SetCgmXDeDivStatWithoutPhase() local156 DividerIndex = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_DIVIDER_INDEX]; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()163 RegValue = Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex]; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()166 Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex] = RegValue; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()169 if((Instance == 0U) && (SelectorIndex == 2U) && (DividerIndex == 2U)) in Clock_Ip_SetCgmXDeDivStatWithoutPhase()173 else if((Instance == 4U) && (SelectorIndex == 2U) && (DividerIndex == 2U)) in Clock_Ip_SetCgmXDeDivStatWithoutPhase()199 … Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex] |= MC_CGM_MUX_DC_DE_MASK; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()203 … Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex] &= ~MC_CGM_MUX_DC_DE_MASK; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()216 (void)DividerIndex; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()233 uint32 DividerIndex; in Clock_Ip_SetPllPll0divDeDivOutput() local[all …]
164 uint8 DividerIndex; in Clock_Ip_ResetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize() local171 for (DividerIndex = 0U; DividerIndex < Clock_Ip_apxPll[Instance].DivsNo; DividerIndex++) in Clock_Ip_ResetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()173 Clock_Ip_apxPll[Instance].PllInstance->PLLODIV[DividerIndex] &= ~PLL_PLLODIV_DE_MASK; in Clock_Ip_ResetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()181 (void)DividerIndex; in Clock_Ip_ResetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()301 uint8 DividerIndex; in Clock_Ip_ResetPllRdivMfiMfnOdiv2Sdmen() local308 for (DividerIndex = 0U; DividerIndex < Clock_Ip_apxPll[Instance].DivsNo; DividerIndex++) in Clock_Ip_ResetPllRdivMfiMfnOdiv2Sdmen()310 Clock_Ip_apxPll[Instance].PllInstance->PLLODIV[DividerIndex] &= ~PLL_PLLODIV_DE_MASK; in Clock_Ip_ResetPllRdivMfiMfnOdiv2Sdmen()318 (void)DividerIndex; in Clock_Ip_ResetPllRdivMfiMfnOdiv2Sdmen()
138 uint32 DividerIndex = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_DIVIDER_INDEX]; in Clock_Ip_SetCgmXDeDivStatWithoutPhase() local153 RegValue = Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex]; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()156 Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex] = RegValue; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()159 if((Instance == 0U) && (SelectorIndex == 2U) && (DividerIndex == 2U)) in Clock_Ip_SetCgmXDeDivStatWithoutPhase()163 else if((Instance == 4U) && (SelectorIndex == 2U) && (DividerIndex == 2U)) in Clock_Ip_SetCgmXDeDivStatWithoutPhase()189 … Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex] |= MC_CGM_MUX_DC_DE_MASK; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()193 … Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex] &= ~MC_CGM_MUX_DC_DE_MASK; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()209 uint32 DividerIndex = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_DIVIDER_INDEX]; in Clock_Ip_SetCgmXDeDivStatWithoutPhaseWithTrigger() local224 RegValue = Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex]; in Clock_Ip_SetCgmXDeDivStatWithoutPhaseWithTrigger()227 Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex] = RegValue; in Clock_Ip_SetCgmXDeDivStatWithoutPhaseWithTrigger()[all …]
139 uint32 DividerIndex = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_DIVIDER_INDEX]; in Clock_Ip_ResetDfsMfiMfn() local142 Clock_Ip_apxDfs[Instance]->PORTRESET |= (1UL << DividerIndex); in Clock_Ip_ResetDfsMfiMfn()148 uint32 DividerIndex = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_DIVIDER_INDEX]; in Clock_Ip_SetDfsMfiMfn() local161 Clock_Ip_apxDfs[Instance]->DVPORT[DividerIndex] = Value; in Clock_Ip_SetDfsMfiMfn()164 Clock_Ip_apxDfs[Instance]->PORTRESET &= ~(1UL << DividerIndex); in Clock_Ip_SetDfsMfiMfn()178 uint32 DividerIndex = Clock_Ip_au8ClockFeatures[DfsName][CLOCK_IP_DIVIDER_INDEX]; in Clock_Ip_CompleteDfsMfiMfn() local181 if (0U == (Clock_Ip_apxDfs[Instance]->PORTRESET & (1UL << DividerIndex))) in Clock_Ip_CompleteDfsMfiMfn()187 …stance]->PORTSR >> DFS_PORTSR_PORTSTAT_SHIFT) & DFS_PORTSR_PORTSTAT_MASK) & (1UL << DividerIndex)); in Clock_Ip_CompleteDfsMfiMfn()
171 uint8 DividerIndex; in Clock_Ip_ResetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize() local174 for (DividerIndex = 0U; DividerIndex < Clock_Ip_apxPll[Instance].DivsNo; DividerIndex++) in Clock_Ip_ResetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()176 Clock_Ip_apxPll[Instance].PllInstance->PLLODIV[DividerIndex] &= ~PLLDIG_PLLODIV_DE_MASK; in Clock_Ip_ResetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()281 uint8 DividerIndex; in Clock_Ip_ResetPlldigRdivMfiMfnSdmen() local284 for (DividerIndex = 0U; DividerIndex < Clock_Ip_apxPll[Instance].DivsNo; DividerIndex++) in Clock_Ip_ResetPlldigRdivMfiMfnSdmen()286 Clock_Ip_apxPll[Instance].PllInstance->PLLODIV[DividerIndex] &= ~PLLDIG_PLLODIV_DE_MASK; in Clock_Ip_ResetPlldigRdivMfiMfnSdmen()
