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Searched refs:DMA0_TRIG6_PIO0_5 (Results 1 – 9 of 9) sorted by relevance

/hal_nxp-3.5.0/dts/nxp/lpc/
DLPC51U68JBD48-pinctrl.h131 #define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ macro
DLPC54114J256UK49-pinctrl.h144 #define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ macro
DLPC51U68JBD64-pinctrl.h190 #define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ macro
DLPC54114J256BD64-pinctrl.h212 #define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ macro
/hal_nxp-3.5.0/dts/nxp/nxp_imx/rt/
DMIMXRT685SFAWBR-pinctrl.h482 #define DMA0_TRIG6_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ macro
DMIMXRT595SFAWC-pinctrl.h566 #define DMA0_TRIG6_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ macro
DMIMXRT595SFFOC-pinctrl.h568 #define DMA0_TRIG6_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ macro
DMIMXRT685SFFOB-pinctrl.h484 #define DMA0_TRIG6_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ macro
DMIMXRT685SFVKB-pinctrl.h484 #define DMA0_TRIG6_PIO0_5 IOPCTL_MUX(5, 0) /* PIO0_5 */ macro