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Searched refs:Clock_Ip_apxPll (Results 1 – 8 of 8) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32k3/Mcu/src/
DClock_Ip_Pll.c171 for (DividerIndex = 0U; DividerIndex < Clock_Ip_apxPll[Instance].DivsNo; DividerIndex++) in Clock_Ip_ResetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
173 Clock_Ip_apxPll[Instance].PllInstance->PLLODIV[DividerIndex] &= ~PLL_PLLODIV_DE_MASK; in Clock_Ip_ResetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
176 Clock_Ip_apxPll[Instance].PllInstance->PLLCR |= PLL_PLLCR_PLLPD_MASK; in Clock_Ip_ResetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
196 Value = Clock_Ip_apxPll[Instance].PllInstance->PLLDV; in Clock_Ip_SetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
200 Clock_Ip_apxPll[Instance].PllInstance->PLLDV = Value; in Clock_Ip_SetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
203 Value = Clock_Ip_apxPll[Instance].PllInstance->PLLFD; in Clock_Ip_SetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
207 Clock_Ip_apxPll[Instance].PllInstance->PLLFD = Value; in Clock_Ip_SetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
214 Clock_Ip_apxPll[Instance].PllInstance->PLLFM = Value; in Clock_Ip_SetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
217 …Clock_Ip_apxPll[Instance].PllInstance->PLLCAL2 = PLL_PLLCAL2_ULKCTL((Config->FrequencyModulationBy… in Clock_Ip_SetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
220 Clock_Ip_apxPll[Instance].PllInstance->PLLCR &= ~PLL_PLLCR_PLLPD_MASK; in Clock_Ip_SetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
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DClock_Ip_Divider.c241 …CLOCK_IP_DEV_ASSERT(!(Clock_Ip_apxPll[Instance].PllInstance->PLLODIV[DividerIndex] & PLL_PLLODIV_D… in Clock_Ip_SetPllPll0divDeDivOutput()
245 RegValue = Clock_Ip_apxPll[Instance].PllInstance->PLLODIV[DividerIndex]; in Clock_Ip_SetPllPll0divDeDivOutput()
249 Clock_Ip_apxPll[Instance].PllInstance->PLLODIV[DividerIndex] = RegValue; in Clock_Ip_SetPllPll0divDeDivOutput()
274 RegValue = Clock_Ip_apxPll[Instance].PllInstance->PLLDV; in Clock_Ip_SetPllPlldvOdiv2Output()
277 Clock_Ip_apxPll[Instance].PllInstance->PLLDV = RegValue; in Clock_Ip_SetPllPlldvOdiv2Output()
DClock_Ip_Data.c3408 Clock_Ip_PllType const Clock_Ip_apxPll[CLOCK_IP_PLL_INSTANCES_ARRAY_SIZE] = { variable
/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Pll.c174 for (DividerIndex = 0U; DividerIndex < Clock_Ip_apxPll[Instance].DivsNo; DividerIndex++) in Clock_Ip_ResetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
176 Clock_Ip_apxPll[Instance].PllInstance->PLLODIV[DividerIndex] &= ~PLLDIG_PLLODIV_DE_MASK; in Clock_Ip_ResetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
180 Clock_Ip_apxPll[Instance].PllInstance->PLLCR |= PLLDIG_PLLCR_PLLPD_MASK; in Clock_Ip_ResetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
194 …Clock_Ip_apxPll[Instance].PllInstance->PLLCLKMUX = PLLDIG_PLLCLKMUX_REFCLKSEL(CLOCK_IP_FIRC_PLL_RE… in Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
198 …Clock_Ip_apxPll[Instance].PllInstance->PLLCLKMUX = PLLDIG_PLLCLKMUX_REFCLKSEL(CLOCK_IP_FXOSC_PLL_R… in Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
208 Clock_Ip_apxPll[Instance].PllInstance->PLLDV = Value; in Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
210 Value = Clock_Ip_apxPll[Instance].PllInstance->PLLFD; in Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
214 Clock_Ip_apxPll[Instance].PllInstance->PLLFD = Value; in Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
220 Clock_Ip_apxPll[Instance].PllInstance->PLLFM = Value; in Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
235 if (0U == (Clock_Ip_apxPll[Instance].PllInstance->PLLCR & PLLDIG_PLLCR_PLLPD_MASK)) in Clock_Ip_CompletePlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
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DClock_Ip_Divider.c273 …CLOCK_IP_DEV_ASSERT(!(Clock_Ip_apxPll[Instance].PllInstance->PLLODIV[DividerIndex] & PLLDIG_PLLODI… in Clock_Ip_SetPlldigPll0divDeDivOutput()
278 RegValue = Clock_Ip_apxPll[Instance].PllInstance->PLLODIV[DividerIndex]; in Clock_Ip_SetPlldigPll0divDeDivOutput()
282 Clock_Ip_apxPll[Instance].PllInstance->PLLODIV[DividerIndex] = RegValue; in Clock_Ip_SetPlldigPll0divDeDivOutput()
DClock_Ip_Data.c2881 Clock_Ip_PllType const Clock_Ip_apxPll[CLOCK_IP_PLL_INSTANCES_ARRAY_SIZE] = { variable
/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/include/
DClock_Ip_Specific.h307 extern Clock_Ip_PllType const Clock_Ip_apxPll[CLOCK_IP_PLL_INSTANCES_ARRAY_SIZE];
/hal_nxp-3.5.0/s32/drivers/s32k3/Mcu/include/
DClock_Ip_Specific.h458 extern Clock_Ip_PllType const Clock_Ip_apxPll[CLOCK_IP_PLL_INSTANCES_ARRAY_SIZE];