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Searched refs:CMU_FC_GCR_FCE_MASK (Results 1 – 6 of 6) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Monitor.c268 if (CLOCK_IP_CMU_FREQUENCY_CHECK_ENABLED == (CmuFc->GCR & CMU_FC_GCR_FCE_MASK)) in Clock_Ip_DisableCmuFcFceRefCntLfrefHfref()
288 CmuFc->GCR &= ~CMU_FC_GCR_FCE_MASK; in Clock_Ip_DisableCmuFcFceRefCntLfrefHfref()
425 if (CLOCK_IP_CMU_FREQUENCY_CHECK_ENABLED == (CmuFc->GCR & CMU_FC_GCR_FCE_MASK)) in Clock_Ip_GetStatusCmuFcFceRefCntLfrefHfref()
452 CmuFc->GCR |= CMU_FC_GCR_FCE_MASK; in Clock_Ip_EnableCmuFcFceRefCntLfrefHfref()
456 CmuFc->GCR &= ~CMU_FC_GCR_FCE_MASK; in Clock_Ip_EnableCmuFcFceRefCntLfrefHfref()
/hal_nxp-3.5.0/s32/drivers/s32k3/Mcu/src/
DClock_Ip_Monitor.c272 if (CLOCK_IP_CMU_FREQUENCY_CHECK_ENABLED == (CmuFc->GCR & CMU_FC_GCR_FCE_MASK)) in Clock_Ip_DisableCmuFcFceRefCntLfrefHfref()
291 CmuFc->GCR &= ~CMU_FC_GCR_FCE_MASK; in Clock_Ip_DisableCmuFcFceRefCntLfrefHfref()
425 CmuFc->GCR |= CMU_FC_GCR_FCE_MASK; in Clock_Ip_EnableCmuFcFceRefCntLfrefHfref()
429 CmuFc->GCR &= ~CMU_FC_GCR_FCE_MASK; in Clock_Ip_EnableCmuFcFceRefCntLfrefHfref()
/hal_nxp-3.5.0/s32/drivers/s32k3/BaseNXP/header/
DS32K344_CMU_FC.h118 #define CMU_FC_GCR_FCE_MASK (0x1U) macro
121 … (((uint32_t)(((uint32_t)(x)) << CMU_FC_GCR_FCE_SHIFT)) & CMU_FC_GCR_FCE_MASK)
/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_CMU_FC.h210 #define CMU_FC_GCR_FCE_MASK (0x1U) macro
213 … (((uint32_t)(((uint32_t)(x)) << CMU_FC_GCR_FCE_SHIFT)) & CMU_FC_GCR_FCE_MASK)
/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/include/
DClock_Ip_Specific.h194 #define CLOCK_IP_CMU_FREQUENCY_CHECK_ENABLED CMU_FC_GCR_FCE_MASK
/hal_nxp-3.5.0/s32/drivers/s32k3/Mcu/include/
DClock_Ip_Specific.h348 #define CLOCK_IP_CMU_FREQUENCY_CHECK_ENABLED CMU_FC_GCR_FCE_MASK