CACHE64_CTRL0 (reference) in projects: hal_nxp-3.5.0

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Searched refs:CACHE64_CTRL0 (Results 1 – 11 of 11) sorted by relevance

/hal_nxp-3.5.0/mcux/mcux-sdk/components/internal_flash/octal_flash/RT595/
D	fsl_adapter_flexspi_nor_flash.c	298 …CACHE64_CTRL0->CCR \|= CACHE64_CTRL_CCR_INVW0_MASK \| CACHE64_CTRL_CCR_INVW1_MASK \| CACHE64_CTRL_CCR… in flexspi_nor_invalid_flexspi_cache() 299 while (CACHE64_CTRL0->CCR & CACHE64_CTRL_CCR_GO_MASK) in flexspi_nor_invalid_flexspi_cache() 302 CACHE64_CTRL0->CCR &= ~(CACHE64_CTRL_CCR_INVW0_MASK \| CACHE64_CTRL_CCR_INVW1_MASK); in flexspi_nor_invalid_flexspi_cache() 351 if (CACHE64_CTRL_CCR_ENCACHE_MASK == (CACHE64_CTRL0->CCR & CACHE64_CTRL_CCR_ENCACHE_MASK)) in HAL_FlashInit() 353 CACHE64_DisableCache(CACHE64_CTRL0); in HAL_FlashInit() 388 CACHE64_EnableCache(CACHE64_CTRL0); in HAL_FlashInit() 470 if (CACHE64_CTRL_CCR_ENCACHE_MASK == (CACHE64_CTRL0->CCR & CACHE64_CTRL_CCR_ENCACHE_MASK)) in HAL_FlashProgram() 472 CACHE64_DisableCache(CACHE64_CTRL0); in HAL_FlashProgram() 555 CACHE64_EnableCache(CACHE64_CTRL0); in HAL_FlashProgram() 600 if (CACHE64_CTRL_CCR_ENCACHE_MASK == (CACHE64_CTRL0->CCR & CACHE64_CTRL_CCR_ENCACHE_MASK)) in HAL_FlashEraseSector() [all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT595S/
D	system_MIMXRT595S_cm33.c	`125 CACHE64_CTRL0->CCR = CACHE64_CTRL_CCR_INVW1_MASK \| CACHE64_CTRL_CCR_INVW0_MASK; in SystemInit() 126 CACHE64_CTRL0->CCR \|= CACHE64_CTRL_CCR_GO_MASK; in SystemInit() 128 while ((CACHE64_CTRL0->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0U) in SystemInit() 132 CACHE64_CTRL0->CCR = (CACHE64_CTRL_CCR_ENWRBUF_MASK \| CACHE64_CTRL_CCR_ENCACHE_MASK); in SystemInit()`
D	MIMXRT595S_cm33.h	`7621 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type )CACHE64_CTRL0_BASE) macro 7635 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0, CACHE64_CTRL1 } 7644 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type )CACHE64_CTRL0_BASE) macro 7652 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0, CACHE64_CTRL1 }`
D	MIMXRT595S_dsp.h	`1470 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro 1478 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0, CACHE64_CTRL1 }`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT555S/
D	system_MIMXRT555S.c	`124 CACHE64_CTRL0->CCR = CACHE64_CTRL_CCR_INVW1_MASK \| CACHE64_CTRL_CCR_INVW0_MASK; in SystemInit() 125 CACHE64_CTRL0->CCR \|= CACHE64_CTRL_CCR_GO_MASK; in SystemInit() 127 while ((CACHE64_CTRL0->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0U) in SystemInit() 131 CACHE64_CTRL0->CCR = (CACHE64_CTRL_CCR_ENWRBUF_MASK \| CACHE64_CTRL_CCR_ENCACHE_MASK); in SystemInit()`
D	MIMXRT555S.h	`7620 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type )CACHE64_CTRL0_BASE) macro 7634 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0, CACHE64_CTRL1 } 7643 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type )CACHE64_CTRL0_BASE) macro 7651 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0, CACHE64_CTRL1 }`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT533S/
D	system_MIMXRT533S.c	`124 CACHE64_CTRL0->CCR = CACHE64_CTRL_CCR_INVW1_MASK \| CACHE64_CTRL_CCR_INVW0_MASK; in SystemInit() 125 CACHE64_CTRL0->CCR \|= CACHE64_CTRL_CCR_GO_MASK; in SystemInit() 127 while ((CACHE64_CTRL0->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0U) in SystemInit() 131 CACHE64_CTRL0->CCR = (CACHE64_CTRL_CCR_ENWRBUF_MASK \| CACHE64_CTRL_CCR_ENCACHE_MASK); in SystemInit()`
D	MIMXRT533S.h	`7617 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type )CACHE64_CTRL0_BASE) macro 7631 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0, CACHE64_CTRL1 } 7640 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type )CACHE64_CTRL0_BASE) macro 7648 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0, CACHE64_CTRL1 }`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5536/
D	LPC5536.h	`2277 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type )CACHE64_CTRL0_BASE) macro 2283 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } 2292 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type )CACHE64_CTRL0_BASE) macro 2296 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 }`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5534/
D	LPC5534.h	`2277 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type )CACHE64_CTRL0_BASE) macro 2283 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } 2292 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type )CACHE64_CTRL0_BASE) macro 2296 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 }`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC55S36/
D	LPC55S36.h	`2276 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type )CACHE64_CTRL0_BASE) macro 2282 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } 2291 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type )CACHE64_CTRL0_BASE) macro 2295 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 }`

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