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Searched refs:SIM_SCGC5_PORTB_MASK (Results 1 – 22 of 22) sorted by relevance

/hal_nxp-2.7.6/mcux/devices/MKW22D5/
Dsystem_MKW22D5.c87 SIM->SCGC5 |= SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK; /* Ungate PORTB and PORTC clock*/ in ExtClk_Setup_HookUp()
DMKW22D5.h6599 #define SIM_SCGC5_PORTB_MASK (0x400U) macro
6601 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW24D5/
Dsystem_MKW24D5.c87 SIM->SCGC5 |= SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK; /* Ungate PORTB and PORTC clock*/ in ExtClk_Setup_HookUp()
DMKW24D5.h6599 #define SIM_SCGC5_PORTB_MASK (0x400U) macro
6601 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW30Z4/
Dsystem_MKW30Z4.c101 SIM->SCGC5 |= SIM_SCGC5_PORTB_MASK; in SystemInit()
DMKW30Z4.h6979 #define SIM_SCGC5_PORTB_MASK 0x400u macro
6982 …) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTB_SHIFT))&SIM_SCGC5_PORTB_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW20Z4/
Dsystem_MKW20Z4.c101 SIM->SCGC5 |= SIM_SCGC5_PORTB_MASK; in SystemInit()
DMKW20Z4.h6979 #define SIM_SCGC5_PORTB_MASK 0x400u macro
6982 …) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTB_SHIFT))&SIM_SCGC5_PORTB_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW40Z4/
Dsystem_MKW40Z4.c101 SIM->SCGC5 |= SIM_SCGC5_PORTB_MASK; in SystemInit()
DMKW40Z4.h6979 #define SIM_SCGC5_PORTB_MASK 0x400u macro
6982 …) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTB_SHIFT))&SIM_SCGC5_PORTB_MASK)
DMKW40Z4_extension.h20061 #define SIM_RD_SCGC5_PORTB(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PORTB_MASK) >> SIM_SCGC5_PORTB_S…
20065 #define SIM_WR_SCGC5_PORTB(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PORTB_MASK, SIM_SCGC5_PORTB(…
/hal_nxp-2.7.6/mcux/devices/MKL25Z4/
DMKL25Z4.h3814 #define SIM_SCGC5_PORTB_MASK (0x400U) macro
3816 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
/hal_nxp-2.7.6/mcux/devices/MK22F51212/
DMK22F51212.h12138 #define SIM_SCGC5_PORTB_MASK (0x400U) macro
12144 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW31Z4/
DMKW31Z4.h6415 #define SIM_SCGC5_PORTB_MASK (0x400U) macro
6417 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
/hal_nxp-2.7.6/mcux/devices/MK64F12/
DMK64F12.h21791 #define SIM_SCGC5_PORTB_MASK (0x400U) macro
21797 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW21Z4/
DMKW21Z4.h6344 #define SIM_SCGC5_PORTB_MASK (0x400U) macro
6346 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW41Z4/
DMKW41Z4.h6415 #define SIM_SCGC5_PORTB_MASK (0x400U) macro
6417 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV56F24/
DMKV56F24.h19765 #define SIM_SCGC5_PORTB_MASK (0x400U) macro
19771 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
/hal_nxp-2.7.6/mcux/devices/MK80F25615/
DMK80F25615.h22256 #define SIM_SCGC5_PORTB_MASK (0x400U) macro
22262 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV58F24/
DMKV58F24.h21105 #define SIM_SCGC5_PORTB_MASK (0x400U) macro
21111 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
/hal_nxp-2.7.6/mcux/devices/MK82F25615/
DMK82F25615.h23236 #define SIM_SCGC5_PORTB_MASK (0x400U) macro
23242 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
/hal_nxp-2.7.6/mcux/devices/MK66F18/
DMK66F18.h22370 #define SIM_SCGC5_PORTB_MASK (0x400U) macro
22376 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)