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Searched refs:FSL_FEATURE_MCG_PLL_VDIV_BASE (Results 1 – 25 of 26) sorted by relevance

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/hal_nxp-2.7.6/mcux/devices/MKL25Z4/
Dfsl_clock.c600 mcgpll0clk *= (FSL_FEATURE_MCG_PLL_VDIV_BASE + MCG_C6_VDIV0_VAL); in CLOCK_GetPll0Freq()
705 …if ((vdiv_cur < FSL_FEATURE_MCG_PLL_VDIV_BASE - 1U) || (vdiv_cur > FSL_FEATURE_MCG_PLL_VDIV_BASE +… in CLOCK_CalcPllDiv()
713 if (vdiv_cur >= FSL_FEATURE_MCG_PLL_VDIV_BASE) in CLOCK_CalcPllDiv()
718 *vdiv = vdiv_cur - FSL_FEATURE_MCG_PLL_VDIV_BASE; in CLOCK_CalcPllDiv()
730 if (vdiv_cur <= (FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) in CLOCK_CalcPllDiv()
747 *vdiv = ret_vdiv - FSL_FEATURE_MCG_PLL_VDIV_BASE; in CLOCK_CalcPllDiv()
DMKL25Z4_features.h1281 #define FSL_FEATURE_MCG_PLL_VDIV_BASE (24) macro
/hal_nxp-2.7.6/mcux/devices/MKW22D5/
Dfsl_clock.c624 mcgpll0clk *= (FSL_FEATURE_MCG_PLL_VDIV_BASE + MCG_C6_VDIV0_VAL); in CLOCK_GetPll0Freq()
758 …if ((vdiv_cur < FSL_FEATURE_MCG_PLL_VDIV_BASE - 1U) || (vdiv_cur > FSL_FEATURE_MCG_PLL_VDIV_BASE +… in CLOCK_CalcPllDiv()
766 if (vdiv_cur >= FSL_FEATURE_MCG_PLL_VDIV_BASE) in CLOCK_CalcPllDiv()
771 *vdiv = vdiv_cur - FSL_FEATURE_MCG_PLL_VDIV_BASE; in CLOCK_CalcPllDiv()
783 if (vdiv_cur <= (FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) in CLOCK_CalcPllDiv()
800 *vdiv = ret_vdiv - FSL_FEATURE_MCG_PLL_VDIV_BASE; in CLOCK_CalcPllDiv()
DMKW22D5_features.h921 #define FSL_FEATURE_MCG_PLL_VDIV_BASE (24) macro
/hal_nxp-2.7.6/mcux/devices/MKW24D5/
Dfsl_clock.c624 mcgpll0clk *= (FSL_FEATURE_MCG_PLL_VDIV_BASE + MCG_C6_VDIV0_VAL); in CLOCK_GetPll0Freq()
758 …if ((vdiv_cur < FSL_FEATURE_MCG_PLL_VDIV_BASE - 1U) || (vdiv_cur > FSL_FEATURE_MCG_PLL_VDIV_BASE +… in CLOCK_CalcPllDiv()
766 if (vdiv_cur >= FSL_FEATURE_MCG_PLL_VDIV_BASE) in CLOCK_CalcPllDiv()
771 *vdiv = vdiv_cur - FSL_FEATURE_MCG_PLL_VDIV_BASE; in CLOCK_CalcPllDiv()
783 if (vdiv_cur <= (FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) in CLOCK_CalcPllDiv()
800 *vdiv = ret_vdiv - FSL_FEATURE_MCG_PLL_VDIV_BASE; in CLOCK_CalcPllDiv()
DMKW24D5_features.h921 #define FSL_FEATURE_MCG_PLL_VDIV_BASE (24) macro
/hal_nxp-2.7.6/mcux/devices/MKV58F24/
Dfsl_clock.c719 mcgpll0vdiv = ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + MCG_C6_VDIV0_VAL); in CLOCK_GetPll0Freq()
878 if ((vdiv_cur < ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE - 1U)) || in CLOCK_CalcPllDiv()
879 (vdiv_cur > (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) in CLOCK_CalcPllDiv()
887 if (vdiv_cur >= (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE) in CLOCK_CalcPllDiv()
892 *vdiv = vdiv_cur - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE; in CLOCK_CalcPllDiv()
904 if (vdiv_cur <= ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) in CLOCK_CalcPllDiv()
921 *vdiv = ret_vdiv - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE; in CLOCK_CalcPllDiv()
/hal_nxp-2.7.6/mcux/devices/MKV56F24/
Dfsl_clock.c719 mcgpll0vdiv = ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + MCG_C6_VDIV0_VAL); in CLOCK_GetPll0Freq()
878 if ((vdiv_cur < ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE - 1U)) || in CLOCK_CalcPllDiv()
879 (vdiv_cur > (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) in CLOCK_CalcPllDiv()
887 if (vdiv_cur >= (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE) in CLOCK_CalcPllDiv()
892 *vdiv = vdiv_cur - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE; in CLOCK_CalcPllDiv()
904 if (vdiv_cur <= ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) in CLOCK_CalcPllDiv()
921 *vdiv = ret_vdiv - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE; in CLOCK_CalcPllDiv()
DMKV56F24_features.h1296 #define FSL_FEATURE_MCG_PLL_VDIV_BASE (16) macro
/hal_nxp-2.7.6/mcux/devices/MK22F51212/
Dfsl_clock.c798 mcgpll0vdiv = ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + MCG_C6_VDIV0_VAL); in CLOCK_GetPll0Freq()
983 if ((vdiv_cur < ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE - 1U)) || in CLOCK_CalcPllDiv()
984 (vdiv_cur > (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) in CLOCK_CalcPllDiv()
992 if (vdiv_cur >= (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE) in CLOCK_CalcPllDiv()
997 *vdiv = vdiv_cur - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE; in CLOCK_CalcPllDiv()
1009 if (vdiv_cur <= ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) in CLOCK_CalcPllDiv()
1026 *vdiv = ret_vdiv - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE; in CLOCK_CalcPllDiv()
DMK22F51212_features.h1411 #define FSL_FEATURE_MCG_PLL_VDIV_BASE (24) macro
/hal_nxp-2.7.6/mcux/devices/MK64F12/
Dfsl_clock.c765 mcgpll0vdiv = ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + MCG_C6_VDIV0_VAL); in CLOCK_GetPll0Freq()
950 if ((vdiv_cur < ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE - 1U)) || in CLOCK_CalcPllDiv()
951 (vdiv_cur > (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) in CLOCK_CalcPllDiv()
959 if (vdiv_cur >= (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE) in CLOCK_CalcPllDiv()
964 *vdiv = vdiv_cur - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE; in CLOCK_CalcPllDiv()
976 if (vdiv_cur <= ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) in CLOCK_CalcPllDiv()
993 *vdiv = ret_vdiv - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE; in CLOCK_CalcPllDiv()
DMK64F12_features.h1166 #define FSL_FEATURE_MCG_PLL_VDIV_BASE (24) macro
/hal_nxp-2.7.6/mcux/devices/MK80F25615/
Dfsl_clock.c804 mcgpll0vdiv = ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + MCG_C6_VDIV0_VAL); in CLOCK_GetPll0Freq()
992 if ((vdiv_cur < ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE - 1U)) || in CLOCK_CalcPllDiv()
993 (vdiv_cur > (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) in CLOCK_CalcPllDiv()
1001 if (vdiv_cur >= (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE) in CLOCK_CalcPllDiv()
1006 *vdiv = vdiv_cur - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE; in CLOCK_CalcPllDiv()
1018 if (vdiv_cur <= ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) in CLOCK_CalcPllDiv()
1035 *vdiv = ret_vdiv - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE; in CLOCK_CalcPllDiv()
DMK80F25615_features.h1376 #define FSL_FEATURE_MCG_PLL_VDIV_BASE (16) macro
/hal_nxp-2.7.6/mcux/devices/MK82F25615/
Dfsl_clock.c804 mcgpll0vdiv = ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + MCG_C6_VDIV0_VAL); in CLOCK_GetPll0Freq()
992 if ((vdiv_cur < ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE - 1U)) || in CLOCK_CalcPllDiv()
993 (vdiv_cur > (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) in CLOCK_CalcPllDiv()
1001 if (vdiv_cur >= (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE) in CLOCK_CalcPllDiv()
1006 *vdiv = vdiv_cur - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE; in CLOCK_CalcPllDiv()
1018 if (vdiv_cur <= ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) in CLOCK_CalcPllDiv()
1035 *vdiv = ret_vdiv - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE; in CLOCK_CalcPllDiv()
DMK82F25615_features.h1393 #define FSL_FEATURE_MCG_PLL_VDIV_BASE (16) macro
/hal_nxp-2.7.6/mcux/devices/MK66F18/
Dfsl_clock.c995 mcgpll0vdiv = ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + MCG_C6_VDIV0_VAL); in CLOCK_GetPll0Freq()
1210 if ((vdiv_cur < ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE - 1U)) || in CLOCK_CalcPllDiv()
1211 (vdiv_cur > (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) in CLOCK_CalcPllDiv()
1219 if (vdiv_cur >= (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE) in CLOCK_CalcPllDiv()
1224 *vdiv = vdiv_cur - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE; in CLOCK_CalcPllDiv()
1236 if (vdiv_cur <= ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) in CLOCK_CalcPllDiv()
1253 *vdiv = ret_vdiv - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE; in CLOCK_CalcPllDiv()
DMK66F18_features.h1134 #define FSL_FEATURE_MCG_PLL_VDIV_BASE (16) macro
/hal_nxp-2.7.6/mcux/devices/MKW30Z4/
DMKW30Z4_features.h900 #define FSL_FEATURE_MCG_PLL_VDIV_BASE (0) macro
/hal_nxp-2.7.6/mcux/devices/MKW20Z4/
DMKW20Z4_features.h900 #define FSL_FEATURE_MCG_PLL_VDIV_BASE (0) macro
/hal_nxp-2.7.6/mcux/devices/MKW40Z4/
DMKW40Z4_features.h900 #define FSL_FEATURE_MCG_PLL_VDIV_BASE (0) macro
/hal_nxp-2.7.6/mcux/devices/MKW21Z4/
DMKW21Z4_features.h1164 #define FSL_FEATURE_MCG_PLL_VDIV_BASE (0) macro
/hal_nxp-2.7.6/mcux/devices/MKW31Z4/
DMKW31Z4_features.h1403 #define FSL_FEATURE_MCG_PLL_VDIV_BASE (0) macro
/hal_nxp-2.7.6/mcux/devices/MKW41Z4/
DMKW41Z4_features.h1403 #define FSL_FEATURE_MCG_PLL_VDIV_BASE (0) macro

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