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Searched refs:C3 (Results 1 – 25 of 34) sorted by relevance

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/hal_nxp-2.7.6/mcux/drivers/kinetis/
Dfsl_uart.c574 base->C3 |= (uint8_t)(mask >> 16); in UART_EnableInterrupts()
602 base->C3 &= ~(uint8_t)(mask >> 16); in UART_DisableInterrupts()
635 temp |= ((uint32_t)(base->C3) << 16); in UART_GetEnabledInterrupts()
995 base->C3 |= ((uint8_t)UART_C3_ORIE_MASK | (uint8_t)UART_C3_FEIE_MASK); in UART_TransferStartRingBuffer()
999 base->C3 |= (uint8_t)UART_C3_PEIE_MASK; in UART_TransferStartRingBuffer()
1022 base->C3 &= ~((uint8_t)UART_C3_ORIE_MASK | (uint8_t)UART_C3_FEIE_MASK); in UART_TransferStopRingBuffer()
1026 base->C3 &= ~(uint8_t)UART_C3_PEIE_MASK; in UART_TransferStopRingBuffer()
1289 base->C3 |= ((uint8_t)UART_C3_ORIE_MASK | (uint8_t)UART_C3_FEIE_MASK); in UART_TransferReceiveNonBlocking()
1294 base->C3 |= (uint8_t)UART_C3_PEIE_MASK; in UART_TransferReceiveNonBlocking()
1332 base->C3 &= ~((uint8_t)UART_C3_ORIE_MASK | (uint8_t)UART_C3_FEIE_MASK); in UART_TransferAbortReceive()
[all …]
Dfsl_spi.c237 rxSize = (base->C3 & SPI_C3_RNFULLF_MARK_MASK) >> SPI_C3_RNFULLF_MARK_SHIFT; in SPI_GetWatermark()
438 … base->C3 = SPI_C3_TNEAREF_MARK(config->txWatermark) | SPI_C3_RNFULLF_MARK(config->rxWatermark) | in SPI_MasterInit()
498 … base->C3 = SPI_C3_TNEAREF_MARK(config->txWatermark) | SPI_C3_RNFULLF_MARK(config->rxWatermark) | in SPI_SlaveInit()
564 base->C3 |= SPI_C3_RNFULLIEN_MASK; in SPI_EnableInterrupts()
570 base->C3 |= SPI_C3_TNEARIEN_MASK; in SPI_EnableInterrupts()
602 base->C3 &= ~SPI_C3_RNFULLIEN_MASK; in SPI_DisableInterrupts()
608 base->C3 &= ~SPI_C3_TNEARIEN_MASK; in SPI_DisableInterrupts()
698 base->C3 |= SPI_C3_FIFOMODE_MASK; in SPI_EnableFIFO()
702 base->C3 &= ~SPI_C3_FIFOMODE_MASK; in SPI_EnableFIFO()
758 base->C3 &= ~SPI_C3_FIFOMODE_MASK; in SPI_MasterTransferBlocking()
Dfsl_lpsci.c439 base->C3 |= (mask >> 16); in LPSCI_EnableInterrupts()
450 base->C3 &= ~(mask >> 16); in LPSCI_DisableInterrupts()
456 temp = base->BDH | ((uint32_t)(base->C2) << 8) | ((uint32_t)(base->C3) << 16); in LPSCI_GetEnabledInterrupts()
Dfsl_uart.h398 base->C3 |= (uint8_t)UART_C3_T8_MASK; in UART_Set9thTransmitBit()
408 base->C3 &= ~(uint8_t)UART_C3_T8_MASK; in UART_Clear9thTransmitBit()
Dfsl_spi_dma.c180 base->C3 &= ~SPI_C3_FIFOMODE_MASK; in SPI_MasterTransferCreateHandleDMA()
Dfsl_acmp.c638 base->C3 = tmp32; in ACMP_SetDiscreteModeConfig()
/hal_nxp-2.7.6/mcux/devices/MKW30Z4/
Dsystem_MKW30Z4.c129 MCG->C3 = *((uint8_t*)SLOW_TRIM_ADDRESS); in SystemInit()
DMKW30Z4.h4317 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */ member
4344 #define MCG_C3_REG(base) ((base)->C3)
/hal_nxp-2.7.6/mcux/devices/MKW20Z4/
Dsystem_MKW20Z4.c129 MCG->C3 = *((uint8_t*)SLOW_TRIM_ADDRESS); in SystemInit()
DMKW20Z4.h4317 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */ member
4344 #define MCG_C3_REG(base) ((base)->C3)
/hal_nxp-2.7.6/mcux/devices/MKW40Z4/
Dsystem_MKW40Z4.c129 MCG->C3 = *((uint8_t*)SLOW_TRIM_ADDRESS); in SystemInit()
DMKW40Z4.h4317 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */ member
4344 #define MCG_C3_REG(base) ((base)->C3)
/hal_nxp-2.7.6/mcux/drivers/imxrt6xx/
Dfsl_acmp.c638 base->C3 = tmp32; in ACMP_SetDiscreteModeConfig()
/hal_nxp-2.7.6/mcux/drivers/imx/
Dfsl_acmp.c638 base->C3 = tmp32; in ACMP_SetDiscreteModeConfig()
Dfsl_pxp.h326 float C3; /*!< C3. */ member
Dfsl_pxp.c567 …(PXP_ConvertFloat(config->C3, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF4… in PXP_SetCsc2Config()
/hal_nxp-2.7.6/mcux/devices/MIMXRT1176/
Dfsl_acmp.c638 base->C3 = tmp32; in ACMP_SetDiscreteModeConfig()
/hal_nxp-2.7.6/mcux/devices/MKL25Z4/
DMKL25Z4.h1997 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */ member
4468 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */ member
4707 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */ member
/hal_nxp-2.7.6/mcux/devices/MK22F51212/
DMK22F51212.h8622 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */ member
13240 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */ member
/hal_nxp-2.7.6/mcux/devices/MKW24D5/
DMKW24D5.h4752 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */ member
7189 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */ member
/hal_nxp-2.7.6/mcux/devices/MKW22D5/
DMKW22D5.h4752 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */ member
7189 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */ member
/hal_nxp-2.7.6/mcux/devices/MK64F12/
DMK64F12.h16484 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */ member
23602 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */ member
/hal_nxp-2.7.6/mcux/devices/MKV56F24/
DMKV56F24.h14918 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */ member
22210 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */ member
/hal_nxp-2.7.6/mcux/devices/MKV58F24/
DMKV58F24.h16258 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */ member
23550 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */ member
/hal_nxp-2.7.6/mcux/devices/MK66F18/
DMK66F18.h16851 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */ member
24553 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */ member

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