Searched refs:BR (Results 1 – 12 of 12) sorted by relevance
303 base->BR[index] = 0; in SEMC_Init()417 base->BR[cs] = (config->address & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK; in SEMC_ConfigureSDRAM()549 base->BR[4] = (config->axiAddress & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK; in SEMC_ConfigureNAND()556 base->BR[8] = (config->ipgAddress & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK; in SEMC_ConfigureNAND()697 base->BR[5] = (config->address & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK; in SEMC_ConfigureNOR()854 base->BR[6] = tempBRVal; in SEMC_ConfigureSRAMWithChipSelection()1059 base->BR[7] = (config->address & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK; in SEMC_ConfigureDBI()
664 base->BR = SPI_BR_SPR(bestDivisor) | SPI_BR_SPPR(bestPrescaler); in SPI_MasterSetBaudRate()
4035 __IO uint8_t BR; /**< SPI baud rate register, offset: 0x2 */ member
33357 …__IO uint32_t BR[9]; /**< Base Register 0 (For SDRAM CS0 device)..Base… member
33339 …__IO uint32_t BR[9]; /**< Base Register 0 (For SDRAM CS0 device)..Base… member
30586 …__IO uint32_t BR[9]; /**< Base Register 0 (For SDRAM CS0 device)..Base… member
38720 …__IO uint32_t BR[9]; /**< Base Register 0 (For SDRAM CS0 device)..Base… member
32826 …__IO uint32_t BR[9]; /**< Base Register 0 (For SDRAM CS0 device)..Base… member
41185 …__IO uint32_t BR[9]; /**< Base Register 0 (For SDRAM CS0 device)..Base… member
41111 …__IO uint32_t BR[9]; /**< Base Register 0 (For SDRAM CS0 device)..Base… member
82879 …__IO uint32_t BR[9]; /**< Base Register 0..Base Register 8, array offs… member
83810 …__IO uint32_t BR[9]; /**< Base Register 0..Base Register 8, array offs… member
