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Searched refs:__HSI (Results 1 – 6 of 6) sorted by relevance

/hal_nuvoton-latest/m2l31x/Devices/M2L31/Source/
Dsystem_M2L31.c21 uint32_t SystemCoreClock = __HSI; /*!< System Clock Frequency (Core Clock) */
22 uint32_t CyclesPerUs = (__HSI / 1000000); /*!< Cycles per micro second */
23 uint32_t PllClock = __HSI; /*!< PLL Output Clock Frequency */
/hal_nuvoton-latest/m46x/Devices/M460/Include/
Dsystem_m460.h24 #ifndef __HSI
25 #define __HSI (12000000UL) /*!< PLL default output is 50MHz */ macro
/hal_nuvoton-latest/m48x/Devices/M480/Source/
Dsystem_M480.c22 uint32_t CyclesPerUs = (__HSI / 1000000UL); /* Cycles per micro second */
23 uint32_t PllClock = __HSI; /*!< PLL Output Clock Frequency */
/hal_nuvoton-latest/m46x/Devices/M460/Source/
Dsystem_M460.c21 uint32_t CyclesPerUs = (__HSI / 1000000UL); /* Cycles per micro second */
22 uint32_t PllClock = __HSI; /*!< PLL Output Clock Frequency */
/hal_nuvoton-latest/m48x/Devices/M480/Include/
Dsystem_M480.h24 #define __HSI (12000000UL) /*!< PLL default output is 50MHz */ macro
/hal_nuvoton-latest/m2l31x/Devices/M2L31/Include/
Dsystem_M2L31.h36 #define __HSI (72000000UL) /*!< Default output is 72MHz for PLL */ macro