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Searched refs:PLLFNCTL0 (Results 1 – 3 of 3) sorted by relevance

/hal_nuvoton-latest/m46x/StdDriver/src/
Dclk.c1716 CLK->PLLFNCTL0 = (u32X << CLK_PLLFNCTL0_FRDIV_Pos) | in CLK_EnablePLLFN()
1730 CLK->PLLFNCTL0 = CLK_PLLCTL_192MHz_HXT; in CLK_EnablePLLFN()
1758 u32PllReg0 = CLK->PLLFNCTL0; in CLK_GetPLLFNClockFreq()
/hal_nuvoton-latest/m46x/Devices/M460/Include/
Dclk_reg.h1502 …__IO uint32_t PLLFNCTL0; /*!< [0x0048] PLLFN Control Register 0 … member
/hal_nuvoton-latest/dts/m46x/
Dclk_reg.h1502 …__IO uint32_t PLLFNCTL0; /*!< [0x0048] PLLFN Control Register 0 …