Searched refs:CTL2 (Results 1 – 11 of 11) sorted by relevance
397 #define EQEI_SET_CRS_MODE(eqei, u32Mode) ((eqei)->CTL2 = ((eqei)->CTL2 & (~EQEI_CTL2_CRS_Msk)…410 #define EQEI_SET_DIRSRC_MODE(eqei, u32Mode) ((eqei)->CTL2 = ((eqei)->CTL2 & (~EQEI_CTL2_DIRSR…
587 …SPIM->CTL2 = (SPIM->CTL2 & ~SPIM_CTL2_DCNUM_Msk) | (((x) & 0x1FUL) << SPIM_CTL2_DCNUM_Pos) | SPIM_…594 #define SPIM_SET_DEFAULT_DCNUM(x) (SPIM->CTL2 &= ~SPIM_CTL2_USETEN_Msk)
584 …SPIM->CTL2 = (SPIM->CTL2 & ~SPIM_CTL2_DCNUM_Msk) | (((x) & 0x1FUL) << SPIM_CTL2_DCNUM_Pos) | SPIM_…591 #define SPIM_SET_DEFAULT_DCNUM(x) (SPIM->CTL2 &= ~SPIM_CTL2_USETEN_Msk)
106 …__IO uint32_t CTL2; /*!< [0x0020] External Bus Interface Bank2 Control Register … member
423 …__IO uint32_t CTL2; /*!< [0x0048] Control Register 2 … member
277 …__IO uint32_t CTL2; /*!< [0x001C] EQEI Controller Control Register2 … member
239 …__IO uint32_t CTL2; /*!< [0x0020] External Bus Interface Bank2 Control Register … member
279 …__IO uint32_t CTL2; /*!< [0x001c] EQEI Controller Control Register2 … member
243 …__IO uint32_t CTL2; /*!< [0x0020] External Bus Interface Bank2 Control Register … member
