Searched refs:CLK_CLKSEL1_UART0SEL_PLL_DIV2 (Results 1 – 2 of 2) sorted by relevance
157 #define CLK_CLKSEL1_UART0SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL1_UART0SEL_Pos) /*!< Select UAR… macro
