Home
last modified time | relevance | path

Searched refs:CLK (Results 1 – 25 of 49) sorted by relevance

12

/hal_nuvoton-latest/m46x/StdDriver/src/
Dclk.c33 CLK->APBCLK0 &= (~CLK_APBCLK0_CLKOCKEN_Msk); in CLK_DisableCKO()
59 … CLK->CLKOCTL = CLK_CLKOCTL_CLKOEN_Msk | (u32ClkDiv) | (u32ClkDivBy1En << CLK_CLKOCTL_DIV1EN_Pos); in CLK_EnableCKO()
62 CLK->APBCLK0 |= CLK_APBCLK0_CLKOCKEN_Msk; in CLK_EnableCKO()
65 CLK->CLKSEL1 = (CLK->CLKSEL1 & (~CLK_CLKSEL1_CLKOSEL_Msk)) | (u32ClkSrc); in CLK_EnableCKO()
83 CLK->PWRCTL |= (CLK_PWRCTL_PDEN_Msk); in CLK_PowerDown()
117 CLK->PWRCTL &= ~CLK_PWRCTL_PDEN_Msk; in CLK_Idle()
133 if(CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk) in CLK_GetHXTFreq()
156 if(CLK->PWRCTL & CLK_PWRCTL_LXTEN_Msk) in CLK_GetLXTFreq()
179 if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_APB0DIV_DIV1) in CLK_GetPCLK0Freq()
183 else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_APB0DIV_DIV2) in CLK_GetPCLK0Freq()
[all …]
Dspi.c76 … CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1; in SPI_Open()
80 … CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK0; in SPI_Open()
84 … CLK->CLKSEL3 = (CLK->CLKSEL3 & (~CLK_CLKSEL3_SPI2SEL_Msk)) | CLK_CLKSEL3_SPI2SEL_PCLK1; in SPI_Open()
88 … CLK->CLKSEL3 = (CLK->CLKSEL3 & (~CLK_CLKSEL3_SPI3SEL_Msk)) | CLK_CLKSEL3_SPI3SEL_PCLK0; in SPI_Open()
92 … CLK->CLKSEL4 = (CLK->CLKSEL4 & (~CLK_CLKSEL4_SPI4SEL_Msk)) | CLK_CLKSEL4_SPI4SEL_PCLK1; in SPI_Open()
96 … CLK->CLKSEL4 = (CLK->CLKSEL4 & (~CLK_CLKSEL4_SPI5SEL_Msk)) | CLK_CLKSEL4_SPI5SEL_PCLK0; in SPI_Open()
100 … CLK->CLKSEL4 = (CLK->CLKSEL4 & (~CLK_CLKSEL4_SPI6SEL_Msk)) | CLK_CLKSEL4_SPI6SEL_PCLK1; in SPI_Open()
104 … CLK->CLKSEL4 = (CLK->CLKSEL4 & (~CLK_CLKSEL4_SPI7SEL_Msk)) | CLK_CLKSEL4_SPI7SEL_PCLK0; in SPI_Open()
108 … CLK->CLKSEL4 = (CLK->CLKSEL4 & (~CLK_CLKSEL4_SPI8SEL_Msk)) | CLK_CLKSEL4_SPI8SEL_PCLK1; in SPI_Open()
112 … CLK->CLKSEL4 = (CLK->CLKSEL4 & (~CLK_CLKSEL4_SPI9SEL_Msk)) | CLK_CLKSEL4_SPI9SEL_PCLK0; in SPI_Open()
[all …]
Duart.c209 … u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk) >> CLK_CLKSEL1_UART0SEL_Pos; in UART_Open()
210 … u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos; in UART_Open()
213 … u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos; in UART_Open()
214 … u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos; in UART_Open()
217 … u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART2SEL_Msk) >> CLK_CLKSEL3_UART2SEL_Pos; in UART_Open()
218 … u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART2DIV_Msk) >> CLK_CLKDIV4_UART2DIV_Pos; in UART_Open()
221 … u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART3SEL_Msk) >> CLK_CLKSEL3_UART3SEL_Pos; in UART_Open()
222 … u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART3DIV_Msk) >> CLK_CLKDIV4_UART3DIV_Pos; in UART_Open()
225 … u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART4SEL_Msk) >> CLK_CLKSEL3_UART4SEL_Pos; in UART_Open()
226 … u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART4DIV_Msk) >> CLK_CLKDIV4_UART4DIV_Pos; in UART_Open()
[all …]
Deadc.c61 u32ClkSel0Backup = CLK->CLKSEL0; in EADC_Open()
62 u32PclkDivBackup = CLK->PCLKDIV; in EADC_Open()
72 u32ClkDivBackup = CLK->CLKDIV0; in EADC_Open()
73 … CLK->CLKDIV0 = (CLK->CLKDIV0 & ~CLK_CLKDIV0_EADC0DIV_Msk) | (2 << CLK_CLKDIV0_EADC0DIV_Pos); in EADC_Open()
74 CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_EADC0SEL_Msk) | CLK_CLKSEL0_EADC0SEL_HCLK; in EADC_Open()
78 u32ClkDivBackup = CLK->CLKDIV2; in EADC_Open()
79 … CLK->CLKDIV2 = (CLK->CLKDIV2 & ~CLK_CLKDIV2_EADC1DIV_Msk) | (2 << CLK_CLKDIV2_EADC1DIV_Pos); in EADC_Open()
80 CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_EADC1SEL_Msk) | CLK_CLKSEL0_EADC1SEL_HCLK; in EADC_Open()
84 u32ClkDivBackup = CLK->CLKDIV5; in EADC_Open()
85 … CLK->CLKDIV5 = (CLK->CLKDIV5 & ~CLK_CLKDIV5_EADC2DIV_Msk) | (2 << CLK_CLKDIV5_EADC2DIV_Pos); in EADC_Open()
[all …]
Dqspi.c71 … CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI0SEL_Msk)) | CLK_CLKSEL2_QSPI0SEL_PCLK0; in QSPI_Open()
73 … CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI1SEL_Msk)) | CLK_CLKSEL2_QSPI1SEL_PCLK1; in QSPI_Open()
79 if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_HXT) in QSPI_Open()
83 else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PLL_DIV2) in QSPI_Open()
87 else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PCLK0) in QSPI_Open()
98 if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI1SEL_Msk) == CLK_CLKSEL2_QSPI1SEL_HXT) in QSPI_Open()
102 else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI1SEL_Msk) == CLK_CLKSEL2_QSPI1SEL_PLL_DIV2) in QSPI_Open()
106 else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI1SEL_Msk) == CLK_CLKSEL2_QSPI1SEL_PCLK1) in QSPI_Open()
169 … CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI0SEL_Msk)) | CLK_CLKSEL2_QSPI0SEL_PCLK0; in QSPI_Open()
175 … CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI1SEL_Msk)) | CLK_CLKSEL2_QSPI1SEL_PCLK1; in QSPI_Open()
[all …]
Drng.c55 CLK->AHBCLK0 |= CLK_AHBCLK0_CRPTCKEN_Msk; in RNG_BasicConfig()
56 CLK->APBCLK1 |= CLK_APBCLK1_TRNGCKEN_Msk; in RNG_BasicConfig()
59 CLK->PWRCTL |= CLK_PWRCTL_LIRCEN_Msk; in RNG_BasicConfig()
60 while((CLK->STATUS & CLK_STATUS_LIRCSTB_Msk) == 0) in RNG_BasicConfig()
64 CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_TRNGSEL_Msk)) | CLK_CLKSEL2_TRNGSEL_LIRC; in RNG_BasicConfig()
Dsdh.c350 u32SD_PwrCtl = CLK->PWRCTL; in SDH_Set_clock()
353 CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk; in SDH_Set_clock()
358 u32SD_ClkSrc = (CLK->CLKSEL0 & CLK_CLKSEL0_SDH0SEL_Msk); in SDH_Set_clock()
359 CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_SDH0SEL_Msk) | CLK_CLKSEL0_SDH0SEL_HIRC; in SDH_Set_clock()
364 u32SD_ClkSrc = (CLK->CLKSEL0 & CLK_CLKSEL0_SDH1SEL_Msk); in SDH_Set_clock()
365 CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_SDH1SEL_Msk) | CLK_CLKSEL0_SDH1SEL_HIRC; in SDH_Set_clock()
372 CLK->PWRCTL = u32SD_PwrCtl; in SDH_Set_clock()
375 CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_SDH0SEL_Msk) | u32SD_ClkSrc; in SDH_Set_clock()
395 CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_SDH1SEL_Msk) | u32SD_ClkSrc; in SDH_Set_clock()
451 CLK->CLKDIV0 &= ~CLK_CLKDIV0_SDH0DIV_Msk; in SDH_Set_clock()
[all …]
Dtimer.c265 u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR0SEL_Msk) >> CLK_CLKSEL1_TMR0SEL_Pos; in TIMER_GetModuleClock()
269 u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR1SEL_Msk) >> CLK_CLKSEL1_TMR1SEL_Pos; in TIMER_GetModuleClock()
273 u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR2SEL_Msk) >> CLK_CLKSEL1_TMR2SEL_Pos; in TIMER_GetModuleClock()
277 u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR3SEL_Msk) >> CLK_CLKSEL1_TMR3SEL_Pos; in TIMER_GetModuleClock()
Dbpwm.c47 u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM0SEL_Msk; in BPWM_ConfigCaptureChannel()
51 u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM1SEL_Msk; in BPWM_ConfigCaptureChannel()
143 u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM0SEL_Msk; in BPWM_ConfigOutputChannel()
147 u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM1SEL_Msk; in BPWM_ConfigOutputChannel()
/hal_nuvoton-latest/m48x/StdDriver/src/
Dclk.c56 … CLK->CLKOCTL = CLK_CLKOCTL_CLKOEN_Msk | (u32ClkDiv) | (u32ClkDivBy1En << CLK_CLKOCTL_DIV1EN_Pos); in CLK_EnableCKO()
80 CLK->PWRCTL |= (CLK_PWRCTL_PDEN_Msk); in CLK_PowerDown()
108 CLK->PWRCTL &= ~CLK_PWRCTL_PDEN_Msk; in CLK_Idle()
124 if((CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk) == CLK_PWRCTL_HXTEN_Msk) in CLK_GetHXTFreq()
146 if((CLK->PWRCTL & CLK_PWRCTL_LXTEN_Msk) == CLK_PWRCTL_LXTEN_Msk) in CLK_GetLXTFreq()
169 if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_APB0DIV_DIV1) in CLK_GetPCLK0Freq()
173 else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_APB0DIV_DIV2) in CLK_GetPCLK0Freq()
177 else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_APB0DIV_DIV4) in CLK_GetPCLK0Freq()
181 else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_APB0DIV_DIV8) in CLK_GetPCLK0Freq()
185 else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_APB0DIV_DIV16) in CLK_GetPCLK0Freq()
[all …]
Dspi.c76 … CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1; in SPI_Open()
80 … CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK0; in SPI_Open()
84 … CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK1; in SPI_Open()
88 … CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI3SEL_Msk)) | CLK_CLKSEL2_SPI3SEL_PCLK0; in SPI_Open()
95 if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT) in SPI_Open()
99 else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL) in SPI_Open()
103 else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK1) in SPI_Open()
115 if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HXT) in SPI_Open()
119 else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PLL) in SPI_Open()
123 else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PCLK0) in SPI_Open()
[all …]
Duart.c202 …u32UartClkSrcSel = ((uint32_t)(CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk)) >> CLK_CLKSEL1_UART0SEL_P… in UART_Open()
204 u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos; in UART_Open()
209 u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos; in UART_Open()
211 u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos; in UART_Open()
216 u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART2SEL_Msk) >> CLK_CLKSEL3_UART2SEL_Pos; in UART_Open()
218 u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART2DIV_Msk) >> CLK_CLKDIV4_UART2DIV_Pos; in UART_Open()
223 u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART3SEL_Msk) >> CLK_CLKSEL3_UART3SEL_Pos; in UART_Open()
225 u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART3DIV_Msk) >> CLK_CLKDIV4_UART3DIV_Pos; in UART_Open()
230 u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART4SEL_Msk) >> CLK_CLKSEL3_UART4SEL_Pos; in UART_Open()
232 u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART4DIV_Msk) >> CLK_CLKDIV4_UART4DIV_Pos; in UART_Open()
[all …]
Dqspi.c71 … CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI0SEL_Msk)) | CLK_CLKSEL2_QSPI0SEL_PCLK0; in QSPI_Open()
73 … CLK->CLKSEL3 = (CLK->CLKSEL3 & (~CLK_CLKSEL3_QSPI1SEL_Msk)) | CLK_CLKSEL3_QSPI1SEL_PCLK1; in QSPI_Open()
79 if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_HXT) in QSPI_Open()
83 else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PLL) in QSPI_Open()
87 else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PCLK0) in QSPI_Open()
99 if((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_HXT) in QSPI_Open()
103 else if((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_PLL) in QSPI_Open()
107 else if((CLK->CLKSEL3 & CLK_CLKSEL3_QSPI1SEL_Msk) == CLK_CLKSEL3_QSPI1SEL_PCLK1) in QSPI_Open()
171 … CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI0SEL_Msk)) | CLK_CLKSEL2_QSPI0SEL_PCLK0; in QSPI_Open()
177 … CLK->CLKSEL3 = (CLK->CLKSEL3 & (~CLK_CLKSEL3_QSPI1SEL_Msk)) | CLK_CLKSEL3_QSPI1SEL_PCLK1; in QSPI_Open()
[all …]
Dsdh.c295 u32SD_PwrCtl = CLK->PWRCTL; in SDH_Set_clock()
298 CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk; in SDH_Set_clock()
303 u32SD_ClkSrc = (CLK->CLKSEL0 & CLK_CLKSEL0_SDH0SEL_Msk); in SDH_Set_clock()
304 CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_SDH0SEL_Msk) | CLK_CLKSEL0_SDH0SEL_HIRC; in SDH_Set_clock()
308 u32SD_ClkSrc = (CLK->CLKSEL0 & CLK_CLKSEL0_SDH1SEL_Msk); in SDH_Set_clock()
309 CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_SDH1SEL_Msk) | CLK_CLKSEL0_SDH1SEL_HIRC; in SDH_Set_clock()
316 CLK->PWRCTL = u32SD_PwrCtl; in SDH_Set_clock()
319 CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_SDH0SEL_Msk) | u32SD_ClkSrc; in SDH_Set_clock()
339 CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_SDH1SEL_Msk) | u32SD_ClkSrc; in SDH_Set_clock()
382 CLK->CLKDIV0 &= ~CLK_CLKDIV0_SDH0DIV_Msk; in SDH_Set_clock()
[all …]
Dtimer.c245 u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR0SEL_Msk) >> CLK_CLKSEL1_TMR0SEL_Pos; in TIMER_GetModuleClock()
249 u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR1SEL_Msk) >> CLK_CLKSEL1_TMR1SEL_Pos; in TIMER_GetModuleClock()
253 u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR2SEL_Msk) >> CLK_CLKSEL1_TMR2SEL_Pos; in TIMER_GetModuleClock()
257 u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR3SEL_Msk) >> CLK_CLKSEL1_TMR3SEL_Pos; in TIMER_GetModuleClock()
/hal_nuvoton-latest/m2l31x/StdDriver/src/
Dclk.c62 … CLK->CLKOCTL = CLK_CLKOCTL_CLKOEN_Msk | (u32ClkDiv) | (u32ClkDivBy1En << CLK_CLKOCTL_DIV1EN_Pos); in CLK_EnableCKO()
86 CLK->PWRCTL |= (CLK_PWRCTL_PDEN_Msk); in CLK_PowerDown()
114 CLK->PWRCTL &= ~CLK_PWRCTL_PDEN_Msk; in CLK_Idle()
130 if((CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk) == CLK_PWRCTL_HXTEN_Msk) in CLK_GetHXTFreq()
152 if((CLK->PWRCTL & CLK_PWRCTL_LXTEN_Msk) == CLK_PWRCTL_LXTEN_Msk) in CLK_GetLXTFreq()
175 if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_APB0DIV_DIV1) in CLK_GetPCLK0Freq()
179 else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_APB0DIV_DIV2) in CLK_GetPCLK0Freq()
183 else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_APB0DIV_DIV4) in CLK_GetPCLK0Freq()
187 else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_APB0DIV_DIV8) in CLK_GetPCLK0Freq()
191 else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_APB0DIV_DIV16) in CLK_GetPCLK0Freq()
[all …]
Duart.c211 …u32UartClkSrcSel = ((uint32_t)(CLK->CLKSEL4 & CLK_CLKSEL4_UART0SEL_Msk)) >> CLK_CLKSEL4_UART0SEL_P… in UART_Open()
213 u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos; in UART_Open()
218 u32UartClkSrcSel = (CLK->CLKSEL4 & CLK_CLKSEL4_UART1SEL_Msk) >> CLK_CLKSEL4_UART1SEL_Pos; in UART_Open()
220 u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos; in UART_Open()
225 u32UartClkSrcSel = (CLK->CLKSEL4 & CLK_CLKSEL4_UART2SEL_Msk) >> CLK_CLKSEL4_UART2SEL_Pos; in UART_Open()
227 u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART2DIV_Msk) >> CLK_CLKDIV4_UART2DIV_Pos; in UART_Open()
232 u32UartClkSrcSel = (CLK->CLKSEL4 & CLK_CLKSEL4_UART3SEL_Msk) >> CLK_CLKSEL4_UART3SEL_Pos; in UART_Open()
234 u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART3DIV_Msk) >> CLK_CLKDIV4_UART3DIV_Pos; in UART_Open()
239 u32UartClkSrcSel = (CLK->CLKSEL4 & CLK_CLKSEL4_UART4SEL_Msk) >> CLK_CLKSEL4_UART4SEL_Pos; in UART_Open()
241 u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART4DIV_Msk) >> CLK_CLKDIV4_UART4DIV_Pos; in UART_Open()
[all …]
Dspi.c75 … CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1; in SPI_Open()
79 … CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK0; in SPI_Open()
83 … CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL3_SPI2SEL_Msk)) | CLK_CLKSEL3_SPI2SEL_PCLK1; in SPI_Open()
87 … CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL3_SPI3SEL_Msk)) | CLK_CLKSEL3_SPI3SEL_PCLK0; in SPI_Open()
94 if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT) in SPI_Open()
98 else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL) in SPI_Open()
102 else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK1) in SPI_Open()
114 if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HXT) in SPI_Open()
118 else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PLL) in SPI_Open()
122 else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PCLK0) in SPI_Open()
[all …]
Dqspi.c70 … CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI0SEL_Msk)) | CLK_CLKSEL2_QSPI0SEL_PCLK0; in QSPI_Open()
74 if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_HXT) in QSPI_Open()
78 else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PLL) in QSPI_Open()
82 else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PCLK0) in QSPI_Open()
142 CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI0SEL_Msk)) | CLK_CLKSEL2_QSPI0SEL_PCLK0; in QSPI_Open()
234 CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI0SEL_Msk)) | CLK_CLKSEL2_QSPI0SEL_PCLK0; in QSPI_SetBusClock()
238 if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_HXT) in QSPI_SetBusClock()
242 else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PLL) in QSPI_SetBusClock()
246 else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PCLK0) in QSPI_SetBusClock()
327 if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_HXT) in QSPI_GetBusClock()
[all …]
Dtimer.c277 u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR0SEL_Msk) >> CLK_CLKSEL1_TMR0SEL_Pos; in TIMER_GetModuleClock()
281 u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR1SEL_Msk) >> CLK_CLKSEL1_TMR1SEL_Pos; in TIMER_GetModuleClock()
285 u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR2SEL_Msk) >> CLK_CLKSEL1_TMR2SEL_Pos; in TIMER_GetModuleClock()
289 u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR3SEL_Msk) >> CLK_CLKSEL1_TMR3SEL_Pos; in TIMER_GetModuleClock()
/hal_nuvoton-latest/m46x/Devices/M460/Source/
Dsystem_M460.c36 u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk; in SystemCoreClockUpdate()
49 u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1UL; in SystemCoreClockUpdate()
88 CLK->PWRCTL &= ~CLK_PWRCTL_HXTSELTYP_Msk; in SystemInit()
92 CLK->AHBCLK0 |= CLK_AHBCLK0_HBICKEN_Msk; in SystemInit()
113 CLK->AHBCLK0 |= CLK_AHBCLK0_GPCCKEN_Msk | CLK_AHBCLK0_GPGCKEN_Msk; in SystemInit()
136 CLK->AHBCLK0 |= CLK_AHBCLK0_GPDCKEN_Msk | CLK_AHBCLK0_GPHCKEN_Msk; in SystemInit()
137 CLK->AHBCLK1 |= CLK_AHBCLK1_GPJCKEN_Msk; in SystemInit()
/hal_nuvoton-latest/m48x/Devices/M480/Source/
Dsystem_M480.c37 u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk; in SystemCoreClockUpdate()
50 u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1UL; in SystemCoreClockUpdate()
99 CLK->LDOCTL |= CLK_LDOCTL_PDBIASEN_Msk; in SystemInit()
101 CLK->APBCLK0 |= CLK_APBCLK0_RTCCKEN_Msk; in SystemInit()
106 CLK->APBCLK0 &= ~CLK_APBCLK0_RTCCKEN_Msk; in SystemInit()
/hal_nuvoton-latest/m2l31x/StdDriver/inc/
Dclk.h548 #define CLK_DISABLE_DPDWKPIN(void) (CLK->PMUWKCTL &= ~CLK_PMUWKCTL_WKPINEN0_Msk) /*!< Disable …
549 #define CLK_DISABLE_DPDWKPIN0(void) (CLK->PMUWKCTL &= ~CLK_PMUWKCTL_WKPINEN0_Msk) /*!< Disable …
550 #define CLK_DISABLE_DPDWKPIN1(void) (CLK->PMUWKCTL &= ~CLK_PMUWKCTL_WKPINEN1_Msk) /*!< Disable …
551 #define CLK_DISABLE_DPDWKPIN2(void) (CLK->PMUWKCTL &= ~CLK_PMUWKCTL_WKPINEN2_Msk) /*!< Disable …
552 #define CLK_DISABLE_DPDWKPIN3(void) (CLK->PMUWKCTL &= ~CLK_PMUWKCTL_WKPINEN3_Msk) /*!< Disable …
553 #define CLK_DISABLE_DPDWKPIN4(void) (CLK->PMUWKCTL &= ~CLK_PMUWKCTL_WKPINEN4_Msk) /*!< Disable …
554 #define CLK_DISABLE_DPDWKPIN5(void) (CLK->PMUWKCTL &= ~CLK_PMUWKCTL_WKPINEN5_Msk) /*!< Disable …
555 #define CLK_DISABLE_SPDACMP(void) (CLK->PMUWKCTL &= ~CLK_PMUWKCTL_ACMPWKEN_Msk) /*!< Disable …
556 #define CLK_ENABLE_SPDACMP(void) (CLK->PMUWKCTL |= CLK_PMUWKCTL_ACMPWKEN_Msk) /*!< Enable A…
557 #define CLK_DISABLE_RTCWK(void) (CLK->PMUWKCTL &= ~CLK_PMUWKCTL_RTCWKEN_Msk) /*!< Disable …
[all …]
/hal_nuvoton-latest/m48x/StdDriver/inc/
Dclk.h522 #define CLK_DISABLE_WKTMR(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKTMREN_Msk) /*!< Disable Wake…
523 #define CLK_ENABLE_WKTMR(void) (CLK->PMUCTL |= CLK_PMUCTL_WKTMREN_Msk) /*!< Enable Wake-…
524 #define CLK_DISABLE_DPDWKPIN(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN_Msk) /*!< Disable Wake…
525 #define CLK_DISABLE_DPDWKPIN0(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN_Msk) /*!< Disable Wake…
526 #define CLK_DISABLE_DPDWKPIN1(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN1_Msk) /*!< Disable Wake…
527 #define CLK_DISABLE_DPDWKPIN2(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN2_Msk) /*!< Disable Wake…
528 #define CLK_DISABLE_DPDWKPIN3(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN3_Msk) /*!< Disable Wake…
529 #define CLK_DISABLE_DPDWKPIN4(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN4_Msk) /*!< Disable Wake…
530 #define CLK_DISABLE_SPDACMP(void) (CLK->PMUCTL &= ~CLK_PMUCTL_ACMPSPWK_Msk) /*!< Disable ACMP…
531 #define CLK_ENABLE_SPDACMP(void) (CLK->PMUCTL |= CLK_PMUCTL_ACMPSPWK_Msk) /*!< Enable ACMP …
[all …]
/hal_nuvoton-latest/m2l31x/Devices/M2L31/Source/
Dsystem_M2L31.c42 u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLK0SEL_Msk; in SystemCoreClockUpdate()
58 u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLK0DIV_Msk) + 1; in SystemCoreClockUpdate()

12