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Searched refs:APBCLK0 (Results 1 – 9 of 9) sorted by relevance

/hal_nuvoton-latest/m48x/Devices/M480/Source/
Dsystem_M480.c101 CLK->APBCLK0 |= CLK_APBCLK0_RTCCKEN_Msk; in SystemInit()
106 CLK->APBCLK0 &= ~CLK_APBCLK0_RTCCKEN_Msk; in SystemInit()
/hal_nuvoton-latest/m46x/StdDriver/src/
Dclk.c33 CLK->APBCLK0 &= (~CLK_APBCLK0_CLKOCKEN_Msk); in CLK_DisableCKO()
62 CLK->APBCLK0 |= CLK_APBCLK0_CLKOCKEN_Msk; in CLK_EnableCKO()
680 uint32_t u32RTCCKEN = CLK->APBCLK0 & CLK_APBCLK0_RTCCKEN_Msk; in CLK_SetModuleClock()
686 CLK->APBCLK0 |= CLK_APBCLK0_RTCCKEN_Msk; /* Enable RTC clock to get LXT clock source */ in CLK_SetModuleClock()
694 … CLK->APBCLK0 &= (~CLK_APBCLK0_RTCCKEN_Msk); /* Disable RTC clock if it is disabled before */ in CLK_SetModuleClock()
1511 uint32_t u32RTCCKEN = CLK->APBCLK0 & CLK_APBCLK0_RTCCKEN_Msk; in CLK_GetModuleClockSource()
1519 CLK->APBCLK0 |= CLK_APBCLK0_RTCCKEN_Msk; in CLK_GetModuleClockSource()
1527 CLK->APBCLK0 &= (~CLK_APBCLK0_RTCCKEN_Msk); in CLK_GetModuleClockSource()
Drtc.c98 CLK->APBCLK0 &= ~CLK_APBCLK0_RTCCKEN_Msk; in RTC_Close()
/hal_nuvoton-latest/m48x/Devices/M480/Include/
Dclk_reg.h987 …__IO uint32_t APBCLK0; /*!< [0x0008] APB Devices Clock Enable Control Register 0 … member
/hal_nuvoton-latest/m2l31x/Devices/M2L31/Include/
Dclk_reg.h1491 …__IO uint32_t APBCLK0; /*!< [0x0008] APB Devices Clock Enable Control Register 0 … member
/hal_nuvoton-latest/m2l31x/StdDriver/src/
Drtc.c103 CLK->APBCLK0 &= ~CLK_APBCLK0_RTCCKEN_Msk; in RTC_Close()
/hal_nuvoton-latest/m46x/Devices/M460/Include/
Dclk_reg.h1486 …__IO uint32_t APBCLK0; /*!< [0x0008] APB Devices Clock Enable Control Register 0 … member
/hal_nuvoton-latest/m48x/StdDriver/src/
Drtc.c99 CLK->APBCLK0 &= ~CLK_APBCLK0_RTCCKEN_Msk; in RTC_Close()
/hal_nuvoton-latest/dts/m46x/
Dclk_reg.h1486 …__IO uint32_t APBCLK0; /*!< [0x0008] APB Devices Clock Enable Control Register 0 …