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Searched refs:CLK_CLKSEL1_TMR0SEL_Pos (Results 1 – 11 of 11) sorted by relevance

/hal_nuvoton-3.7.0/m48x/StdDriver/inc/
Dclk.h96 #define CLK_CLKSEL1_TMR0SEL_HXT (0x0UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR…
97 #define CLK_CLKSEL1_TMR0SEL_LXT (0x1UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR…
98 #define CLK_CLKSEL1_TMR0SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR…
99 #define CLK_CLKSEL1_TMR0SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR…
100 #define CLK_CLKSEL1_TMR0SEL_PCLK0 (0x2UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR…
101 #define CLK_CLKSEL1_TMR0SEL_EXT (0x3UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR…
/hal_nuvoton-3.7.0/m2l31x/StdDriver/inc/
Dclk.h128 #define CLK_CLKSEL1_TMR0SEL_HXT (0x0UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR…
129 #define CLK_CLKSEL1_TMR0SEL_LXT (0x1UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR…
130 #define CLK_CLKSEL1_TMR0SEL_PCLK0 (0x2UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR…
131 #define CLK_CLKSEL1_TMR0SEL_EXT (0x3UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR…
132 #define CLK_CLKSEL1_TMR0SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR…
133 #define CLK_CLKSEL1_TMR0SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR…
/hal_nuvoton-3.7.0/dts/m46x/
Dclk.h128 #define CLK_CLKSEL1_TMR0SEL_HXT (0x0UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR…
129 #define CLK_CLKSEL1_TMR0SEL_LXT (0x1UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR…
130 #define CLK_CLKSEL1_TMR0SEL_PCLK0 (0x2UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR…
131 #define CLK_CLKSEL1_TMR0SEL_EXT (0x3UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR…
132 #define CLK_CLKSEL1_TMR0SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR…
133 #define CLK_CLKSEL1_TMR0SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR…
Dclk_reg.h1862 #define CLK_CLKSEL1_TMR0SEL_Pos (8) /*!< CLK… macro
1863 #define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos) /*!< CLK…
/hal_nuvoton-3.7.0/m46x/StdDriver/inc/
Dclk.h128 #define CLK_CLKSEL1_TMR0SEL_HXT (0x0UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR…
129 #define CLK_CLKSEL1_TMR0SEL_LXT (0x1UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR…
130 #define CLK_CLKSEL1_TMR0SEL_PCLK0 (0x2UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR…
131 #define CLK_CLKSEL1_TMR0SEL_EXT (0x3UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR…
132 #define CLK_CLKSEL1_TMR0SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR…
133 #define CLK_CLKSEL1_TMR0SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR…
/hal_nuvoton-3.7.0/m48x/Devices/M480/Include/
Dclk_reg.h1290 #define CLK_CLKSEL1_TMR0SEL_Pos (8) /*!< CLK… macro
1291 #define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos) /*!< CLK…
/hal_nuvoton-3.7.0/m48x/StdDriver/src/
Dtimer.c245 u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR0SEL_Msk) >> CLK_CLKSEL1_TMR0SEL_Pos; in TIMER_GetModuleClock()
/hal_nuvoton-3.7.0/m46x/StdDriver/src/
Dtimer.c265 u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR0SEL_Msk) >> CLK_CLKSEL1_TMR0SEL_Pos; in TIMER_GetModuleClock()
/hal_nuvoton-3.7.0/m2l31x/StdDriver/src/
Dtimer.c277 u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR0SEL_Msk) >> CLK_CLKSEL1_TMR0SEL_Pos; in TIMER_GetModuleClock()
/hal_nuvoton-3.7.0/m2l31x/Devices/M2L31/Include/
Dclk_reg.h1783 #define CLK_CLKSEL1_TMR0SEL_Pos (8) /*!< CLK… macro
1784 #define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos) /*!< CLK…
/hal_nuvoton-3.7.0/m46x/Devices/M460/Include/
Dclk_reg.h1861 #define CLK_CLKSEL1_TMR0SEL_Pos (8) /*!< CLK… macro
1862 #define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos) /*!< CLK…