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Searched refs:CLKDIV5 (Results 1 – 8 of 8) sorted by relevance

/hal_nuvoton-3.7.0/m46x/StdDriver/src/
Deadc.c84 u32ClkDivBackup = CLK->CLKDIV5; in EADC_Open()
85 … CLK->CLKDIV5 = (CLK->CLKDIV5 & ~CLK_CLKDIV5_EADC2DIV_Msk) | (2 << CLK_CLKDIV5_EADC2DIV_Pos); in EADC_Open()
116 CLK->CLKDIV5 = u32ClkDivBackup; in EADC_Open()
143 if (u32Apb1Div > ((CLK->CLKDIV5 & CLK_CLKDIV5_EADC2DIV_Msk) >> CLK_CLKDIV5_EADC2DIV_Pos)) in EADC_Open()
Duart.c242 … u32UartClkDivNum = (CLK->CLKDIV5 & CLK_CLKDIV5_UART8DIV_Msk) >> CLK_CLKDIV5_UART8DIV_Pos; in UART_Open()
246 … u32UartClkDivNum = (CLK->CLKDIV5 & CLK_CLKDIV5_UART9DIV_Msk) >> CLK_CLKDIV5_UART9DIV_Pos; in UART_Open()
400 … u32UartClkDivNum = (CLK->CLKDIV5 & CLK_CLKDIV5_UART8DIV_Msk) >> CLK_CLKDIV5_UART8DIV_Pos; in UART_SetLineConfig()
404 … u32UartClkDivNum = (CLK->CLKDIV5 & CLK_CLKDIV5_UART9DIV_Msk) >> CLK_CLKDIV5_UART9DIV_Pos; in UART_SetLineConfig()
515 … u32UartClkDivNum = (CLK->CLKDIV5 & CLK_CLKDIV5_UART8DIV_Msk) >> CLK_CLKDIV5_UART8DIV_Pos; in UART_SelectIrDAMode()
519 … u32UartClkDivNum = (CLK->CLKDIV5 & CLK_CLKDIV5_UART9DIV_Msk) >> CLK_CLKDIV5_UART9DIV_Pos; in UART_SelectIrDAMode()
Dcanfd.c389 …CLK->CLKDIV5 = (CLK->CLKDIV5 & ~CLK_CLKDIV5_CANFD0DIV_Msk) | CLK_CLKDIV5_CANFD0(psConfig->u8PreDiv… in CANFD_SetTimingConfig()
394 …CLK->CLKDIV5 = (CLK->CLKDIV5 & ~CLK_CLKDIV5_CANFD1DIV_Msk) | CLK_CLKDIV5_CANFD1(psConfig->u8PreDiv… in CANFD_SetTimingConfig()
399 …CLK->CLKDIV5 = (CLK->CLKDIV5 & ~CLK_CLKDIV5_CANFD2DIV_Msk) | CLK_CLKDIV5_CANFD2(psConfig->u8PreDiv… in CANFD_SetTimingConfig()
404 …CLK->CLKDIV5 = (CLK->CLKDIV5 & ~CLK_CLKDIV5_CANFD3DIV_Msk) | CLK_CLKDIV5_CANFD3(psConfig->u8PreDiv… in CANFD_SetTimingConfig()
Dclk.c713 …case EADC2_MODULE: CLK->CLKDIV5 = (CLK->CLKDIV5 & (~CLK_CLKDIV5_EADC2DIV_Msk)) | (u32ClkDiv); bre… in CLK_SetModuleClock()
1598 …case EADC2_MODULE: u32DivVal = (CLK->CLKDIV5 & CLK_CLKDIV5_EADC2DIV_Msk) >> CLK_CLKDIV5_EADC2DIV_P… in CLK_GetModuleClockDivider()
/hal_nuvoton-3.7.0/m2l31x/StdDriver/src/
Dcanfd.c370 …CLK->CLKDIV5 = (CLK->CLKDIV5 & ~CLK_CLKDIV5_CANFD0DIV_Msk) | CLK_CLKDIV5_CANFD0(psConfig->u8PreDiv… in CANFD_SetTimingConfig()
375 …CLK->CLKDIV5 = (CLK->CLKDIV5 & ~CLK_CLKDIV5_CANFD1DIV_Msk) | CLK_CLKDIV5_CANFD1(psConfig->u8PreDiv… in CANFD_SetTimingConfig()
/hal_nuvoton-3.7.0/m2l31x/Devices/M2L31/Include/
Dclk_reg.h1502 …__IO uint32_t CLKDIV5; /*!< [0x003c] Clock Divider Number Register 5 … member
/hal_nuvoton-3.7.0/m46x/Devices/M460/Include/
Dclk_reg.h1499 …__IO uint32_t CLKDIV5; /*!< [0x003c] Clock Divider Number Register 5 … member
/hal_nuvoton-3.7.0/dts/m46x/
Dclk_reg.h1499 …__IO uint32_t CLKDIV5; /*!< [0x003c] Clock Divider Number Register 5 …