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Searched refs:CLKDIV0 (Results 1 – 19 of 19) sorted by relevance

/hal_nuvoton-3.7.0/m2l31x/StdDriver/src/
Dclk.c272 u32Hclk1Div = (LPSCC->CLKDIV0 & LPSCC_CLKDIV0_HCLK1DIV_Msk) >> LPSCC_CLKDIV0_HCLK1DIV_Pos; in CLK_GetHCLK1Freq()
296 if((LPSCC->CLKDIV0 & LPSCC_CLKDIV0_APB2DIV_Msk) == LPSCC_CLKDIV0_PCLK2DIV1) in CLK_GetPCLK2Freq()
300 else if((LPSCC->CLKDIV0 & LPSCC_CLKDIV0_APB2DIV_Msk) == LPSCC_CLKDIV0_PCLK2DIV2) in CLK_GetPCLK2Freq()
304 else if((LPSCC->CLKDIV0 & LPSCC_CLKDIV0_APB2DIV_Msk) == LPSCC_CLKDIV0_PCLK2DIV4) in CLK_GetPCLK2Freq()
308 else if((LPSCC->CLKDIV0 & LPSCC_CLKDIV0_APB2DIV_Msk) == LPSCC_CLKDIV0_PCLK2DIV8) in CLK_GetPCLK2Freq()
312 else if((LPSCC->CLKDIV0 & LPSCC_CLKDIV0_APB2DIV_Msk) == LPSCC_CLKDIV0_PCLK2DIV16) in CLK_GetPCLK2Freq()
361 CLK->CLKDIV0 &= (~CLK_CLKDIV0_HCLK0DIV_Msk); in CLK_SetCoreClock()
424 CLK->CLKDIV0 = (CLK->CLKDIV0 & (~CLK_CLKDIV0_HCLK0DIV_Msk)) | u32ClkDiv; in CLK_SetHCLK()
643 u32div = (uint32_t)&LPSCC->CLKDIV0; in CLK_SetModuleClock()
647 u32div = (uint32_t)&CLK->CLKDIV0 + (u32DivTbl[MODULE_CLKDIV(u32ModuleIdx)]); in CLK_SetModuleClock()
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Duart.c213 u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos; in UART_Open()
220 u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos; in UART_Open()
383 u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos; in UART_SetLine_Config()
390 u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos; in UART_SetLine_Config()
512 u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos; in UART_SelectIrDAMode()
519 u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos; in UART_SelectIrDAMode()
Dlpuart.c194 …u32UartClkDivNum = (LPSCC->CLKDIV0 & LPSCC_CLKDIV0_LPUART0DIV_Msk) >> LPSCC_CLKDIV0_LPUART0DIV_Pos; in LPUART_Open()
310 …u32UartClkDivNum = (LPSCC->CLKDIV0 & LPSCC_CLKDIV0_LPUART0DIV_Msk) >> LPSCC_CLKDIV0_LPUART0DIV_Pos; in LPUART_SetLine_Config()
/hal_nuvoton-3.7.0/m46x/StdDriver/src/
Deadc.c72 u32ClkDivBackup = CLK->CLKDIV0; in EADC_Open()
73 … CLK->CLKDIV0 = (CLK->CLKDIV0 & ~CLK_CLKDIV0_EADC0DIV_Msk) | (2 << CLK_CLKDIV0_EADC0DIV_Pos); in EADC_Open()
108 CLK->CLKDIV0 = u32ClkDivBackup; in EADC_Open()
129 if (u32Apb1Div > ((CLK->CLKDIV0 & CLK_CLKDIV0_EADC0DIV_Msk) >> CLK_CLKDIV0_EADC0DIV_Pos)) in EADC_Open()
Dclk.c303 CLK->CLKDIV0 &= (~CLK_CLKDIV0_HCLKDIV_Msk); in CLK_SetCoreClock()
374 CLK->CLKDIV0 = (CLK->CLKDIV0 & (~CLK_CLKDIV0_HCLKDIV_Msk)) | u32ClkDiv; in CLK_SetHCLK()
703 …case EADC0_MODULE: CLK->CLKDIV0 = (CLK->CLKDIV0 & (~CLK_CLKDIV0_EADC0DIV_Msk)) | (u32ClkDiv); bre… in CLK_SetModuleClock()
704 …case SDH0_MODULE: CLK->CLKDIV0 = (CLK->CLKDIV0 & (~CLK_CLKDIV0_SDH0DIV_Msk)) | (u32ClkDiv); bre… in CLK_SetModuleClock()
721 u32Div = (uint32_t)&CLK->CLKDIV0 + (au32DivTbl[MODULE_CLKDIV(u32ModuleIdx)]); in CLK_SetModuleClock()
1588 …case EADC0_MODULE: u32DivVal = (CLK->CLKDIV0 & CLK_CLKDIV0_EADC0DIV_Msk) >> CLK_CLKDIV0_EADC0DIV_P… in CLK_GetModuleClockDivider()
1589 …case SDH0_MODULE: u32DivVal = (CLK->CLKDIV0 & CLK_CLKDIV0_SDH0DIV_Msk) >> CLK_CLKDIV0_SDH0DIV_Pos… in CLK_GetModuleClockDivider()
1604 u32DivAddr = (uint32_t)&CLK->CLKDIV0 + (au32DivTbl[MODULE_CLKDIV(u32ModuleIdx)]); in CLK_GetModuleClockDivider()
Duart.c210 … u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos; in UART_Open()
214 … u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos; in UART_Open()
368 … u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos; in UART_SetLineConfig()
372 … u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos; in UART_SetLineConfig()
483 … u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos; in UART_SelectIrDAMode()
487 … u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos; in UART_SelectIrDAMode()
Dsdh.c451 CLK->CLKDIV0 &= ~CLK_CLKDIV0_SDH0DIV_Msk; in SDH_Set_clock()
452 CLK->CLKDIV0 |= (div1 << CLK_CLKDIV0_SDH0DIV_Pos); in SDH_Set_clock()
/hal_nuvoton-3.7.0/m48x/StdDriver/src/
Duart.c204 u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos; in UART_Open()
211 u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos; in UART_Open()
360 u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos; in UART_SetLineConfig()
367 u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos; in UART_SetLineConfig()
475 u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos; in UART_SelectIrDAMode()
482 u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos; in UART_SelectIrDAMode()
Dclk.c288 CLK->CLKDIV0 &= (~CLK_CLKDIV0_HCLKDIV_Msk); in CLK_SetCoreClock()
346 CLK->CLKDIV0 = (CLK->CLKDIV0 & (~CLK_CLKDIV0_HCLKDIV_Msk)) | u32ClkDiv; in CLK_SetHCLK()
530 u32div = (uint32_t)&CLK->CLKDIV0 + ((MODULE_CLKDIV(u32ModuleIdx)) * 4U); in CLK_SetModuleClock()
546 u32div = (uint32_t)&CLK->CLKDIV0 + ((MODULE_CLKDIV(u32ModuleIdx)) * 4U); in CLK_SetModuleClock()
1331 u32div = (uint32_t)&CLK->CLKDIV0 + (u32DivTbl[MODULE_CLKDIV(u32ModuleIdx)]); in CLK_GetModuleClockDivider()
Dsdh.c382 CLK->CLKDIV0 &= ~CLK_CLKDIV0_SDH0DIV_Msk; in SDH_Set_clock()
383 CLK->CLKDIV0 |= (div1 << CLK_CLKDIV0_SDH0DIV_Pos); in SDH_Set_clock()
/hal_nuvoton-3.7.0/m2l31x/Devices/M2L31/Source/
Dsystem_M2L31.c58 u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLK0DIV_Msk) + 1; in SystemCoreClockUpdate()
/hal_nuvoton-3.7.0/m48x/Devices/M480/Source/
Dsystem_M480.c50 u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1UL; in SystemCoreClockUpdate()
/hal_nuvoton-3.7.0/m46x/Devices/M460/Source/
Dsystem_M460.c49 u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1UL; in SystemCoreClockUpdate()
/hal_nuvoton-3.7.0/m48x/Devices/M480/Include/
Dclk_reg.h993 …__IO uint32_t CLKDIV0; /*!< [0x0020] Clock Divider Number Register 0 … member
/hal_nuvoton-3.7.0/m2l31x/Devices/M2L31/Include/
Dclk_reg.h1497 …__IO uint32_t CLKDIV0; /*!< [0x0020] Clock Divider Number Register 0 … member
Dsys_reg.h324 …__IO uint32_t CLKDIV0; /*!< [0x0060] Peripheral Clock Divider Number Register 0 … member
/hal_nuvoton-3.7.0/m46x/Devices/M460/Include/
Dclk_reg.h1492 …__IO uint32_t CLKDIV0; /*!< [0x0020] Clock Divider Number Register 0 … member
/hal_nuvoton-3.7.0/dts/m46x/
Dclk_reg.h1492 …__IO uint32_t CLKDIV0; /*!< [0x0020] Clock Divider Number Register 0 …
/hal_nuvoton-3.7.0/dts/m2l31x/
Dsys_reg.h324 …__IO uint32_t CLKDIV0; /*!< [0x0060] Peripheral Clock Divider Number Register 0 …