Searched refs:EMAC (Results 1 – 3 of 3) sorted by relevance
153 EMAC->MIIMDAT = u32Data ; in EMAC_MdioWrite()155 …EMAC->MIIMCTL = u32Reg | (u32Addr << 8) | EMAC_MIIMCTL_BUSY_Msk | EMAC_MIIMCTL_WRITE_Msk | EMAC_MI… in EMAC_MdioWrite()158 while (EMAC->MIIMCTL & EMAC_MIIMCTL_BUSY_Msk) in EMAC_MdioWrite()174 …EMAC->MIIMCTL = u32Reg | (u32Addr << EMAC_MIIMCTL_PHYADDR_Pos) | EMAC_MIIMCTL_BUSY_Msk | EMAC_MIIM… in EMAC_MdioRead()177 while (EMAC->MIIMCTL & EMAC_MIIMCTL_BUSY_Msk) in EMAC_MdioRead()183 return EMAC->MIIMDAT; in EMAC_MdioRead()214 EMAC->CTL &= ~EMAC_CTL_OPMODE_Msk; in EMAC_PhyInit()215 EMAC->CTL &= ~EMAC_CTL_FUDUP_Msk; in EMAC_PhyInit()248 EMAC->CTL |= EMAC_CTL_OPMODE_Msk; in EMAC_PhyInit()249 EMAC->CTL |= EMAC_CTL_FUDUP_Msk; in EMAC_PhyInit()[all …]
57 #define EMAC_ENABLE_TX() (EMAC->CTL |= EMAC_CTL_TXON_Msk)66 #define EMAC_ENABLE_RX() do{EMAC->CTL |= EMAC_CTL_RXON_Msk; EMAC->RXST = 0;}while(0)74 #define EMAC_DISABLE_TX() (EMAC->CTL &= ~EMAC_CTL_TXON_Msk)83 #define EMAC_DISABLE_RX() (EMAC->CTL &= ~EMAC_CTL_RXON_Msk)91 #define EMAC_ENABLE_MAGIC_PKT_WAKEUP() (EMAC->CTL |= EMAC_CTL_WOLEN_Msk)99 #define EMAC_DISABLE_MAGIC_PKT_WAKEUP() (EMAC->CTL &= ~EMAC_CTL_WOLEN_Msk)107 #define EMAC_ENABLE_RECV_BCASTPKT() (EMAC->CAMCTL |= EMAC_CAMCTL_ABP_Msk)115 #define EMAC_DISABLE_RECV_BCASTPKT() (EMAC->CAMCTL &= ~EMAC_CAMCTL_ABP_Msk)123 #define EMAC_ENABLE_RECV_MCASTPKT() (EMAC->CAMCTL |= EMAC_CAMCTL_AMP_Msk)131 #define EMAC_DISABLE_RECV_MCASTPKT() (EMAC->CAMCTL &= ~EMAC_CAMCTL_AMP_Msk)[all …]
390 #define EMAC ((EMAC_T *) EMAC_BASE) macro
