153     EMAC->MIIMDAT = u32Data ;  in EMAC_MdioWrite()
155 …EMAC->MIIMCTL = u32Reg | (u32Addr << 8) | EMAC_MIIMCTL_BUSY_Msk | EMAC_MIIMCTL_WRITE_Msk | EMAC_MI…  in EMAC_MdioWrite()
158     while (EMAC->MIIMCTL & EMAC_MIIMCTL_BUSY_Msk)  in EMAC_MdioWrite()
174 …EMAC->MIIMCTL = u32Reg | (u32Addr << EMAC_MIIMCTL_PHYADDR_Pos) | EMAC_MIIMCTL_BUSY_Msk | EMAC_MIIM…  in EMAC_MdioRead()
177     while (EMAC->MIIMCTL & EMAC_MIIMCTL_BUSY_Msk)  in EMAC_MdioRead()
183     return EMAC->MIIMDAT;  in EMAC_MdioRead()
214             EMAC->CTL &= ~EMAC_CTL_OPMODE_Msk;  in EMAC_PhyInit()
215             EMAC->CTL &= ~EMAC_CTL_FUDUP_Msk;  in EMAC_PhyInit()
248             EMAC->CTL |= EMAC_CTL_OPMODE_Msk;  in EMAC_PhyInit()
249             EMAC->CTL |= EMAC_CTL_FUDUP_Msk;  in EMAC_PhyInit()
253             EMAC->CTL |= EMAC_CTL_OPMODE_Msk;  in EMAC_PhyInit()
254             EMAC->CTL &= ~EMAC_CTL_FUDUP_Msk;  in EMAC_PhyInit()
258             EMAC->CTL &= ~EMAC_CTL_OPMODE_Msk;  in EMAC_PhyInit()
259             EMAC->CTL |= EMAC_CTL_FUDUP_Msk;  in EMAC_PhyInit()
263             EMAC->CTL &= ~EMAC_CTL_OPMODE_Msk;  in EMAC_PhyInit()
264             EMAC->CTL &= ~EMAC_CTL_FUDUP_Msk;  in EMAC_PhyInit()
279     EMAC->TXDSA = (uint32_t)&tx_desc[0];  in EMAC_TxDescInit()
316     EMAC->RXDSA = (uint32_t)&rx_desc[0];  in EMAC_RxDescInit()
391     EMAC->INTEN = EMAC_INTEN_RXIEN_Msk |  in EMAC_Open()
402     EMAC->CTL = EMAC_CTL_STRIPCRC_Msk |  in EMAC_Open()
406     EMAC->CAMCTL =  EMAC_CAMCTL_CMPEN_Msk |  in EMAC_Open()
411     EMAC->MRFL = EMAC_MAX_PKT_SIZE;  in EMAC_Open()
422     EMAC->CTL |= EMAC_CTL_RST_Msk;  in EMAC_Close()
424     while (EMAC->CTL & EMAC_CTL_RST_Msk) {}  in EMAC_Close()
455     reg = (uint32_t)&EMAC->CAM0M + u32Entry * 2UL * 4UL;  in EMAC_EnableCamEntry()
457     reg = (uint32_t)&EMAC->CAM0L + u32Entry * 2UL * 4UL;  in EMAC_EnableCamEntry()
460     EMAC->CAMEN |= (1UL << u32Entry);  in EMAC_EnableCamEntry()
470     EMAC->CAMEN &= ~(1UL << u32Entry);  in EMAC_DisableCamEntry()
490     reg = EMAC->INTSTS;  in EMAC_RecvPkt()
491     EMAC->INTSTS = reg & 0xFFFFUL;  /* Clear all RX related interrupt status */  in EMAC_RecvPkt()
555     reg = EMAC->INTSTS;  in EMAC_RecvPktTS()
556     EMAC->INTSTS = reg & 0xFFFFUL; /* Clear all Rx related interrupt status */  in EMAC_RecvPktTS()
570         if (EMAC->CRXDSA != (uint32_t)desc)  in EMAC_RecvPktTS()
693     reg = EMAC->INTSTS;  in EMAC_SendPktDone()
695     EMAC->INTSTS = reg & (0xFFFF0000UL & ~EMAC_INTSTS_TSALMIF_Msk);  in EMAC_SendPktDone()
706         last_tx_desc = EMAC->CTXDSA ;  in EMAC_SendPktDone()
776     reg = EMAC->INTSTS;  in EMAC_SendPktDoneTS()
778     EMAC->INTSTS = reg & (0xFFFF0000UL & ~EMAC_INTSTS_TSALMIF_Msk);  in EMAC_SendPktDoneTS()
848     EMAC->TSCTL = EMAC_TSCTL_TSEN_Msk;  in EMAC_EnableTS()
849     EMAC->UPDSEC = u32Sec;   /* Assume current time is 0 sec + 0 nano sec */  in EMAC_EnableTS()
850     EMAC->UPDSUBSEC = EMAC_Nsec2Subsec(u32Nsec);  in EMAC_EnableTS()
861     EMAC->TSINC = (reg = (uint32_t)f);  in EMAC_EnableTS()
863     EMAC->TSADDEND = (uint32_t)f;  in EMAC_EnableTS()
864 …EMAC->TSCTL |= (EMAC_TSCTL_TSUPDATE_Msk | EMAC_TSCTL_TSIEN_Msk | EMAC_TSCTL_TSMODE_Msk); /* Fine u…  in EMAC_EnableTS()
874     EMAC->TSCTL = 0UL;  in EMAC_DisableTS()
886     *pu32Nsec = EMAC_Subsec2Nsec(EMAC->TSSUBSEC);  in EMAC_GetTime()
887     *pu32Sec = EMAC->TSSEC;  in EMAC_GetTime()
899     EMAC->TSCTL = EMAC_TSCTL_TSEN_Msk;  in EMAC_SetTime()
900     EMAC->UPDSEC = u32Sec;  in EMAC_SetTime()
901     EMAC->UPDSUBSEC = EMAC_Nsec2Subsec(u32Nsec);  in EMAC_SetTime()
902     EMAC->TSCTL |= (EMAC_TSCTL_TSIEN_Msk | EMAC_TSCTL_TSMODE_Msk);  in EMAC_SetTime()
915     EMAC->ALMSEC = u32Sec;  in EMAC_EnableAlarm()
916     EMAC->ALMSUBSEC = EMAC_Nsec2Subsec(u32Nsec);  in EMAC_EnableAlarm()
917     EMAC->TSCTL |= EMAC_TSCTL_TSALMEN_Msk;  in EMAC_EnableAlarm()
929     EMAC->TSCTL &= ~EMAC_TSCTL_TSALMEN_Msk;  in EMAC_DisableAlarm()
942     EMAC->UPDSEC = u32Sec;  in EMAC_UpdateTime()
943     EMAC->UPDSUBSEC = EMAC_Nsec2Subsec(u32Nsec);  in EMAC_UpdateTime()
947         EMAC->UPDSUBSEC |= BIT31;   /* Set bit 31 indicates this is a negative value */  in EMAC_UpdateTime()
950     EMAC->TSCTL |= EMAC_TSCTL_TSUPDATE_Msk;  in EMAC_UpdateTime()
977             EMAC->CTL |= EMAC_CTL_OPMODE_Msk;  in EMAC_CheckLinkStatus()
978             EMAC->CTL |= EMAC_CTL_FUDUP_Msk;  in EMAC_CheckLinkStatus()
983             EMAC->CTL |= EMAC_CTL_OPMODE_Msk;  in EMAC_CheckLinkStatus()
984             EMAC->CTL &= ~EMAC_CTL_FUDUP_Msk;  in EMAC_CheckLinkStatus()
989             EMAC->CTL &= ~EMAC_CTL_OPMODE_Msk;  in EMAC_CheckLinkStatus()
990             EMAC->CTL |= EMAC_CTL_FUDUP_Msk;  in EMAC_CheckLinkStatus()
995             EMAC->CTL &= ~EMAC_CTL_OPMODE_Msk;  in EMAC_CheckLinkStatus()
996             EMAC->CTL &= ~EMAC_CTL_FUDUP_Msk;  in EMAC_CheckLinkStatus()
1020         EMAC_CAMxM = (uint32_t *)((uint32_t)&EMAC->CAM0M + (index * 8));  in EMAC_FillCamEntry()
1021         EMAC_CAMxL = (uint32_t *)((uint32_t)&EMAC->CAM0L + (index * 8));  in EMAC_FillCamEntry()